ise编程顺序.txt

FPGA向CY7C68013接收发送数据的代码,可以用LED显示

1.File->New Project... 注意工程所在的各级目录名应为英文且无空格 Top-Level Module Type: HDL, then select the device&design flow

2.Project->New Source, VHDL module, File Name:Top, write the source file

3.Save then Synthesize-XST

4.添加约束文件 Project->New SOurce, Implementation Constraints FIle, File Name: ucf, connect it to top.vhdl

5.User COnstraints->Edit Constraints(Text)
NET "clk" LOC = "p80";

6.Save all files

7.Generate Programming File

8.Configure Device(iMPACT)