top_clk分频.txt

来自「FPGA向CY7C68013接收发送数据的代码,可以用LED显示」· 文本 代码 · 共 59 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  port( clk  : in std_logic;
        slwr: buffer std_logic;
	   pktend: out std_logic;
	   fifoaddr: out std_logic_vector(1 downto 0);
	   fifodata: out std_logic_vector(7 downto 0);
        full_flag : in std_logic	  -- FLAGB pin
	   ) ;       
end top;

architecture Behavioral of top is

signal  i   : std_logic_vector(7 downto 0):="00000000";
signal  count : std_logic_vector(5 downto 0);
signal  inclk: std_logic;
signal flag,inslwr:   std_logic;

begin

process(clk)
  begin
    	if clk'event and clk='1' then
	  count<=count+'1'; 
	end if;
end process;

fifoaddr<="10";	-- EP6
slwr<=inclk and inslwr;
inclk<=count(5);
pktend<='1';	
flag<=full_flag; 	--and start;

process(inclk)
begin
    if(inclk'event and inclk='0') then

     if flag='1' then	   -- check full flag

		fifodata<=i;	   -- not full, drive data to bus
		inslwr<='1';      -- assert then deassert SLWR
		i<=i+'1';
			 
     else 
	  	inslwr<='0';
     end if;

    end if;
end process;
end 	 Behavioral;