top.syr

FPGA向CY7C68013接收发送数据的代码,可以用LED显示

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl.
WARNING:Xst:1306 - Output <fifodata> is never assigned.
    Found 1-bit register for signal <inclk>.
    Found 1-bit register for signal <inslwr>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...
Loading device for application Xst from file '3s400.nph' in environment C:/Program Files/ISE6.2.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 2

Cell Usage :
# BELS                             : 4
#      GND                         : 1
#      LUT1                        : 1
#      LUT2                        : 1
#      VCC                         : 1
# FlipFlops/Latches                : 2
#      FDR                         : 1
#      FDR_1                       : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 1
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                       2  out of   3584     0%  
 Number of Slice Flip Flops:             2  out of   7168     0%  
 Number of 4 input LUTs:                 2  out of   7168     0%  
 Number of bonded IOBs:                  5  out of    141     3%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
inclk:Q                            | NONE                   | 1     |
clk                                | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 0.577ns (Maximum Frequency: 1733.102MHz)
   Minimum input arrival time before clock: 1.121ns
   Maximum output required time after clock: 6.397ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               0.577ns (Levels of Logic = 0)
  Source:            inclk (FF)
  Destination:       inclk (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: inclk to inclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.000   0.577  inclk (inclk)
     FDR:R                     0.000          inclk
    ----------------------------------------
    Total                      0.577ns (0.000ns logic, 0.577ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'inclk:Q'
Offset:              1.121ns (Levels of Logic = 2)
  Source:            full_flag (PAD)
  Destination:       inslwr (FF)
  Destination Clock: inclk:Q falling

  Data Path: full_flag to inslwr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.641   0.240  full_flag_IBUF (full_flag_IBUF)
     LUT1:I0->O            1   0.000   0.240  inslwr_Sclr_INV1 (inslwr_N17)
     FDR_1:R                   0.000          inslwr
    ----------------------------------------
    Total                      1.121ns (0.641ns logic, 0.480ns route)
                                       (57.2% logic, 42.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.397ns (Levels of Logic = 2)
  Source:            inclk (FF)
  Destination:       slwr (PAD)
  Source Clock:      clk rising

  Data Path: inclk to slwr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.000   0.577  inclk (inclk)
     LUT2:I0->O            1   0.000   0.240  slwr1 (slwr_OBUF)
     OBUF:I->O                 5.580          slwr_OBUF (slwr)
    ----------------------------------------
    Total                      6.397ns (5.580ns logic, 0.817ns route)
                                       (87.2% logic, 12.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'inclk:Q'
Offset:              6.060ns (Levels of Logic = 2)
  Source:            inslwr (FF)
  Destination:       slwr (PAD)
  Source Clock:      inclk:Q falling

  Data Path: inslwr to slwr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            1   0.000   0.240  inslwr (inslwr)
     LUT2:I1->O            1   0.000   0.240  slwr1 (slwr_OBUF)
     OBUF:I->O                 5.580          slwr_OBUF (slwr)
    ----------------------------------------
    Total                      6.060ns (5.580ns logic, 0.480ns route)
                                       (92.1% logic, 7.9% route)

=========================================================================
CPU : 5.00 / 5.95 s | Elapsed : 5.00 / 6.00 s
 
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Total memory usage is 70464 kilobytes