cis_cpld.rpt

用s3c44b0x和 CIS（ContactImage Sensor) 传感器接口

                           Logic cells placed in LAB 'G'
        +----------------- LC98 |COUNTER1:407|COUNT4
        | +--------------- LC106 |COUNTER1:407|COUNT5
        | | +------------- LC111 |COUNTER1:407|COUNT6
        | | | +----------- LC102 |COUNTER1:407|COUNT7
        | | | | +--------- LC101 RAM_D6~1
        | | | | | +------- LC97 /RAM_WR
        | | | | | | +----- LC109 |TEST3:328|:29
        | | | | | | | +--- LC100 |TEST3:328|:40
        | | | | | | | | +- LC103 :353
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC98 -> * * * * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT4
LC106-> - * * * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT5
LC111-> - - * * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT6

Pin
84   -> - - - - - - - - * | - - - - - - * - | <-- /ACK
25   -> - - - - * * - - - | - * - * * * * - | <-- /CPU_CS2
23   -> - - - - * * - - - | - - - - - * * - | <-- /CPU_WR
76   -> - - - - - - - - * | - - - - - - * - | <-- /SENSOR_IN
75   -> * * * * - * - - - | * * - - - - * * | <-- TCLK
LC117-> * * * * - - - - - | * * - - - - * * | <-- CIS_SP
LC116-> * * * * - - - - - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC126-> * * * * - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT1
LC4  -> * * * * - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT2
LC12 -> * * * * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT3
LC128-> * * * * - - - - - | * * - - - - * * | <-- /IRQ1
LC119-> - - - - - - * - - | - - - - - - * - | <-- |TEST3:328|:26
LC123-> - - - - - - - * - | - - - - - - * - | <-- |TEST3:328|:32


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC121 AK_CLK
        | +----------------------------- LC120 AK_TRIG
        | | +--------------------------- LC118 CIS_CLK
        | | | +------------------------- LC117 CIS_SP
        | | | | +----------------------- LC116 |COUNTER1:407|COUNT0
        | | | | | +--------------------- LC126 |COUNTER1:407|COUNT1
        | | | | | | +------------------- LC128 /IRQ1
        | | | | | | | +----------------- LC122 |TEST3:328|:23
        | | | | | | | | +--------------- LC119 |TEST3:328|:26
        | | | | | | | | | +------------- LC123 |TEST3:328|:32
        | | | | | | | | | | +----------- LC114 :281
        | | | | | | | | | | | +--------- LC113 :288
        | | | | | | | | | | | | +------- LC125 |74161:276|p74161:sub|QD
        | | | | | | | | | | | | | +----- LC127 |74161:276|p74161:sub|QC
        | | | | | | | | | | | | | | +--- LC115 |74161:276|p74161:sub|QB
        | | | | | | | | | | | | | | | +- LC124 |74161:276|p74161:sub|QA
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC121-> * * - * - - - - - - - - * * * * | - - - - - - - * | <-- AK_CLK
LC117-> - - - - * * * - - - - - - - - - | * * - - - - * * | <-- CIS_SP
LC116-> - - - - * * - - - - - - - - - - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC128-> - - - - * * - - - - - - - - - - | * * - - - - * * | <-- /IRQ1
LC122-> - - - - - - - * * - - - - - - - | - - - - - - - * | <-- |TEST3:328|:23
LC114-> - * - * - - - - - - - * - - - - | - - - - - - - * | <-- :281
LC113-> - * - * - - - - - - - - - - - - | - - - - - - - * | <-- :288
LC125-> - - * - - - - * - - * * * * - - | - - - - - - - * | <-- |74161:276|p74161:sub|QD
LC127-> - - * - - - - * - - * * * * - - | - - - - - - - * | <-- |74161:276|p74161:sub|QC
LC115-> - - * - - - - * - - * * * * * - | - - - - - - - * | <-- |74161:276|p74161:sub|QB
LC124-> - - * - - - - * - - * * * * * * | - - - - - - - * | <-- |74161:276|p74161:sub|QA

Pin
81   -> * - - - - - - - - - - - - - - - | - - - - - - - * | <-- MCLK
75   -> - - - - * * - - - - - - - - - - | * * - - - - * * | <-- TCLK
LC39 -> - - - - - - - - - - * - - - - - | - - - - - - - * | <-- |TEST3:328|COUNTER:44|temp
LC109-> - - - - - - - - - * - - - - - - | - - - - - - - * | <-- |TEST3:328|:29
LC103-> - - - - - - * - - - - - - - - - | - - - - - - - * | <-- :353


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** EQUATIONS **

CMOS_D0  : INPUT;
CMOS_D1  : INPUT;
CMOS_D2  : INPUT;
CMOS_D3  : INPUT;
CMOS_D4  : INPUT;
CMOS_D5  : INPUT;
CMOS_D6  : INPUT;
CMOS_D7  : INPUT;
CPU_A0   : INPUT;
CPU_A1   : INPUT;
CPU_A2   : INPUT;
CPU_A3   : INPUT;
CPU_A4   : INPUT;
CPU_A5   : INPUT;
CPU_A6   : INPUT;
CPU_A7   : INPUT;
CPU_A8   : INPUT;
CPU_A9   : INPUT;
CPU_A10  : INPUT;
CPU_A11  : INPUT;
CPU_A12  : INPUT;
CPU_A13  : INPUT;
CPU_A19  : INPUT;
CPU_A20  : INPUT;
MCLK     : INPUT;
TCLK     : INPUT;
/ACK     : INPUT;
/CPU_CS1 : INPUT;
/CPU_CS2 : INPUT;
/CPU_RD  : INPUT;
/CPU_WR  : INPUT;
/SENSOR_IN : INPUT;
/TRIG-A  : INPUT;

-- Node name is 'AK_CLK' = ':273' 
-- Equation name is 'AK_CLK', type is output 
 AK_CLK  = TFFE( VCC,  MCLK,  VCC,  VCC,  VCC);

-- Node name is 'AK_TRIG' = '~291~1' 
-- Equation name is 'AK_TRIG', location is LC120, type is output.
 AK_TRIG = DFFE( _EQ001 $  VCC, !AK_CLK,  VCC,  VCC,  VCC);
  _EQ001 = !_LC113 &  _LC114;

-- Node name is 'CIS_CLK' 
-- Equation name is 'CIS_CLK', location is LC118, type is output.
 CIS_CLK = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC115 &  _LC124 &  _LC125 &  _LC127;

-- Node name is 'CIS_SP' = ':291' 
-- Equation name is 'CIS_SP', type is output 
CIS_SP   = _LC117~NOT;
_LC117~NOT = DFFE_HIGH( _EQ001 $  GND, !AK_CLK,  VCC,  VCC,  VCC);

-- Node name is 'CPU_D0' 
-- Equation name is 'CPU_D0', location is LC016, type is bidir.
CPU_D0   = TRI(_LC016,  _LC019);
_LC016   = LCELL( RAM_D0 $  GND);

-- Node name is 'CPU_D1' 
-- Equation name is 'CPU_D1', location is LC014, type is bidir.
CPU_D1   = TRI(_LC014,  _LC019);
_LC014   = LCELL( RAM_D1 $  GND);

-- Node name is 'CPU_D2' 
-- Equation name is 'CPU_D2', location is LC013, type is bidir.
CPU_D2   = TRI(_LC013,  _LC019);
_LC013   = LCELL( RAM_D2 $  GND);

-- Node name is 'CPU_D3' 
-- Equation name is 'CPU_D3', location is LC011, type is bidir.
CPU_D3   = TRI(_LC011,  _LC019);
_LC011   = LCELL( RAM_D3 $  GND);

-- Node name is 'CPU_D4' 
-- Equation name is 'CPU_D4', location is LC009, type is bidir.
CPU_D4   = TRI(_LC009,  _LC019);
_LC009   = LCELL( RAM_D4 $  GND);

-- Node name is 'CPU_D5' 
-- Equation name is 'CPU_D5', location is LC008, type is bidir.
CPU_D5   = TRI(_LC008,  _LC019);
_LC008   = LCELL( RAM_D5 $  GND);

-- Node name is 'CPU_D6' 
-- Equation name is 'CPU_D6', location is LC006, type is bidir.
CPU_D6   = TRI(_LC006,  _LC019);
_LC006   = LCELL( RAM_D6 $  GND);

-- Node name is 'CPU_D7~1' 
-- Equation name is 'CPU_D7~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ003 $  GND);
  _EQ003 = !/CPU_CS2 & !/CPU_RD;

-- Node name is 'CPU_D7' 
-- Equation name is 'CPU_D7', location is LC005, type is bidir.
CPU_D7   = TRI(_LC005,  _LC019);
_LC005   = LCELL( RAM_D7 $  GND);

-- Node name is 'RAM_A0' 
-- Equation name is 'RAM_A0', location is LC080, type is output.
 RAM_A0  = LCELL( _EQ004 $  GND);
  _EQ004 =  /CPU_CS2 &  _LC116
         #  CPU_A0 & !/CPU_CS2;

-- Node name is 'RAM_A1' 
-- Equation name is 'RAM_A1', location is LC078, type is output.
 RAM_A1  = LCELL( _EQ005 $  GND);
  _EQ005 =  /CPU_CS2 &  _LC126
         #  CPU_A1 & !/CPU_CS2;

-- Node name is 'RAM_A2' 
-- Equation name is 'RAM_A2', location is LC077, type is output.
 RAM_A2  = LCELL( _EQ006 $  GND);
  _EQ006 =  /CPU_CS2 &  _LC004
         #  CPU_A2 & !/CPU_CS2;

-- Node name is 'RAM_A3' 
-- Equation name is 'RAM_A3', location is LC075, type is output.
 RAM_A3  = LCELL( _EQ007 $  GND);
  _EQ007 =  /CPU_CS2 &  _LC012
         #  CPU_A3 & !/CPU_CS2;

-- Node name is 'RAM_A4' 
-- Equation name is 'RAM_A4', location is LC073, type is output.
 RAM_A4  = LCELL( _EQ008 $  GND);
  _EQ008 =  /CPU_CS2 &  _LC098
         #  CPU_A4 & !/CPU_CS2;

-- Node name is 'RAM_A5' 
-- Equation name is 'RAM_A5', location is LC072, type is output.
 RAM_A5  = LCELL( _EQ009 $  GND);
  _EQ009 =  /CPU_CS2 &  _LC106
         #  CPU_A5 & !/CPU_CS2;

-- Node name is 'RAM_A6' 
-- Equation name is 'RAM_A6', location is LC070, type is output.
 RAM_A6  = LCELL( _EQ010 $  GND);
  _EQ010 =  /CPU_CS2 &  _LC111
         #  CPU_A6 & !/CPU_CS2;

-- Node name is 'RAM_A7' 
-- Equation name is 'RAM_A7', location is LC069, type is output.
 RAM_A7  = LCELL( _EQ011 $  GND);
  _EQ011 =  /CPU_CS2 &  _LC102
         #  CPU_A7 & !/CPU_CS2;

-- Node name is 'RAM_A8' 
-- Equation name is 'RAM_A8', location is LC067, type is output.
 RAM_A8  = LCELL( _EQ012 $  GND);
  _EQ012 =  /CPU_CS2 &  _LC025
         #  CPU_A8 & !/CPU_CS2;

-- Node name is 'RAM_A9' 
-- Equation name is 'RAM_A9', location is LC065, type is output.
 RAM_A9  = LCELL( _EQ013 $  GND);
  _EQ013 =  /CPU_CS2 &  _LC017
         #  CPU_A9 & !/CPU_CS2;

-- Node name is 'RAM_A10' 
-- Equation name is 'RAM_A10', location is LC049, type is output.
 RAM_A10 = LCELL( _EQ014 $  GND);
  _EQ014 =  /CPU_CS2 &  _LC023
         #  CPU_A10 & !/CPU_CS2;

-- Node name is 'RAM_A11' 
-- Equation name is 'RAM_A11', location is LC051, type is output.
 RAM_A11 = LCELL( _EQ015 $  GND);
  _EQ015 =  /CPU_CS2 &  _LC026
         #  CPU_A11 & !/CPU_CS2;

-- Node name is 'RAM_A12'