stopwatch_tb.tf

FPGA-CPLD_DesignTool(example7）

`timescale 1ns/1ns

module testbench;
	reg CLK;
	reg RESET;
	reg STRTSTOP;
	wire [9:0] TENTHSOUT;
	wire [6:0] ONESOUT;
	wire [6:0] TENSOUT;

	stopwatch TX_stopwatch (
		.CLK(CLK),
		.RESET(RESET),
		.STRTSTOP(STRTSTOP),
		.TENTHSOUT(TENTHSOUT),
		.ONESOUT(ONESOUT),
		.TENSOUT(TENSOUT)
	);

initial
begin
	// --------------------
		CLK = 0;
		RESET = 1;
	// --------------------
		RESET = #55 1'b0;
	// --------------------
		RESET = #4000 1'b1;
		RESET = #55  1'b0;
end

initial
begin
	// --------------------		
		STRTSTOP = 1;
	// --------------------
		STRTSTOP = #200 1'b0;
		STRTSTOP = #100 1'b1;
		STRTSTOP = #200 1'b0;
		STRTSTOP = #100 1'b1;
		STRTSTOP = #500 1'b0;
		STRTSTOP = #200 1'b1;
end

always
begin
		CLK = #10 ~CLK;
end
	

endmodule