stopwatch.par

FPGA-CPLD_DesignTool(example7）

Release 5.1.02i - Par F.25
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


      ::  Sat Dec 07 16:30:19 2002


C:/Xilinx/bin/nt/par.exe -w -ol 2 -t 1 stopwatch_map.ncd stopwatch.ncd
stopwatch.pcf 


Constraints file: stopwatch.pcf

Loading device database for application par from file "stopwatch_map.ncd".
   "stopwatch" is an NCD, version 2.37, device xcv300e, package bg432, speed -6
Loading device for application par from file 'v300e.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.68 2002-06-19.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            26 out of 316     8%
      Number of LOCed External IOBs    0 out of 26      0%

   Number of SLICEs                   32 out of 3072    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897a5) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:997734) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file stopwatch.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 2 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 251 unrouted;       REAL time: 3 secs 

Phase 2: 237 unrouted;       REAL time: 3 secs 

Phase 3: 55 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Finished Router          REAL time: 3 secs 

Total REAL time to router completion: 3 secs 
Total CPU time to router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   14   |  0.047     |  0.492      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The Score for this design is: 153


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.062 ns
   The Maximum Pin Delay is:                               4.421 ns
   The Average Connection Delay on the 10 Worst Nets is:   2.360 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         119         126           3           2           1           0


All signals are completely routed.

Total REAL time to par completion: 4 secs 
Total CPU time to par completion: 3 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file stopwatch.ncd.


PAR done.