stopwatch.sprj

来自「FPGA-CPLD_DesignTool(example7）」· SPRJ 代码 · 共 10 行

`timescale 1ns/1ns
`include "smallcntr.v"
`include "cnt60.v"
`include "decode.v"
`include "hex2led.v"
`include "statmach.v"
`include "tenths.v"
`include "stopwatch.v"
`include "C:/Xilinx/verilog/src/iSE/unisim_comp.v"