prescale_counter.v

来自「FPGA-CPLD_DesignTool(example7）」· Verilog 代码 · 共 23 行

module prescale_counter(reset,clk,counter); 
		    
input reset; 	
input clk;	
output[31:0] counter;
reg[31:0] counter; 
 
always @(posedge clk or negedge reset)
	if(!reset)
		counter[1:0]<=0;
	else
		counter[1:0]<=counter[1:0]+1'b1;	 

always @(posedge clk or negedge reset)
	if(!reset)
		counter[31:2]<=0;
	else
		if(counter[1:0]==2'b11)
			counter[31:2]<=counter[31:2]+1'b1;

endmodule