prescale_counter.par

FPGA-CPLD_DesignTool(example7）

Release 5.1.02i - Par F.25
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


      ::  Sat Dec 07 15:49:27 2002


C:/Xilinx/bin/nt/par.exe -w -ol 2 -t 1 prescale_counter_map.ncd
prescale_counter.ncd prescale_counter.pcf 


Constraints file: prescale_counter.pcf

Loading device database for application par from file
"prescale_counter_map.ncd".
   "prescale_counter" is an NCD, version 2.37, device xcv100e, package bg352,
speed -6
Loading device for application par from file 'v100e.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.68 2002-06-19.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            33 out of 196    16%
      Number of LOCed External IOBs    0 out of 33      0%

   Number of SLICEs                   18 out of 1200    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:989742) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
........
Phase 5.8 (Checksum:99afbf) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file prescale_counter.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 142 unrouted;       REAL time: 2 secs 

Phase 2: 124 unrouted;       REAL time: 2 secs 

Phase 3: 16 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Finished Router          REAL time: 2 secs 

Total REAL time to router completion: 2 secs 
Total CPU time to router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   18   |  0.050     |  0.410      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The Score for this design is: 164


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.153 ns
   The Maximum Pin Delay is:                               3.263 ns
   The Average Connection Delay on the 10 Worst Nets is:   2.469 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          82          28          29           3           0           0


All signals are completely routed.

Total REAL time to par completion: 3 secs 
Total CPU time to par completion: 2 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file prescale_counter.ncd.


PAR done.