_info
来自「FPGA-CPLD_DesignTool(example7)」· 代码 · 共 35 行
TXT
35 行
m255ocModel TechnologydH:\My_Designs\prescale_countervglblIFAMRGAX`bCK2PK0fJAiGk2VDbL]YG2GFhLmAAcPD`b9d2w1024550008FC:/Xilinx/verilog/src/glbl.vL0 3OE;L;5.5f;17r131o-93 +libext+.v+.ve+ +define+OVI_Verilog+vprescale_counterIlX4X^z]Z>@bW]mP8W86bT0VTHY6fZU<YGfjLOcM_]Hi@0w1039247566Fprescale_counter_timesim.vL0 20OE;L;5.5f;17r131o-93 +libext+.v+.ve+ +define+OVI_Verilog+vtestbenchIXTN_Ai]0C2F_:UW8>aWVj0VhGfW:390DM[oDMzegDH9`2w1037242053Ftestbench.tfL0 2OE;L;5.5f;17r131o-93
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