prescale_counter.par

FPGA-CPLD_DesignTool(example7）

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

ZHONGXCH::  Fri Jul 09 17:16:07 2004


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 prescale_counter_map.ncd
prescale_counter.ncd prescale_counter.pcf 


Constraints file: prescale_counter.pcf

Loading device database for application Par from file
"prescale_counter_map.ncd".
   "prescale_counter" is an NCD, version 2.38, device xc2s200, package pq208,
speed -6
Loading device for application Par from file 'v200.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <reset> must be placed at site P180.
Resolved that GCLKIOB <clk> must be placed at site P80.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            33 out of 140    23%
      Number of LOCed External IOBs    1 out of 33      3%

   Number of BLOCKRAMs                 3 out of 14     21%
   Number of SLICEs                  531 out of 2352   22%

   Number of BSCANs                    1 out of 1     100%
   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: PATH "FROM U_CLK TO D_CLK"  TIG ;
Finished initial Timing Analysis.  REAL time: 2 secs 


Phase 1.1
Phase 1.1 (Checksum:98af3a) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
...................................................
............
Phase 5.8 (Checksum:a3bef1) REAL time: 4 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 4 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 5 secs 

Writing design to file prescale_counter.ncd.

Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 5 secs 


Phase 1: 3207 unrouted;       REAL time: 6 secs 

Phase 2: 2685 unrouted;       REAL time: 18 secs 

Phase 3: 579 unrouted;       REAL time: 19 secs 

Phase 4: 579 unrouted; (0)      REAL time: 19 secs 

Phase 5: 579 unrouted; (0)      REAL time: 19 secs 

Phase 6: 579 unrouted; (0)      REAL time: 19 secs 

Phase 7: 0 unrouted; (0)      REAL time: 20 secs 

Total REAL time to Router completion: 20 secs 
Total CPU time to Router completion: 19 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |  211   |  0.353     |  0.540      |
+----------------------------+----------+--------+------------+-------------+
|  icon_control0<0>          |  Global  |  174   |  0.355     |  0.542      |
+----------------------------+----------+--------+------------+-------------+
|  U_icon_pro/iupdate_out    |   Local  |    1   |  0.000     |  1.628      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 194


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.221
   The MAXIMUM PIN DELAY IS:                               4.704
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.578

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1478        1323         328          74           4           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns   | 12.225ns   | 5    
   TO TIMEGRP "J_CLK" 30 nS                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 5.945ns    | 1    
   TO TIMEGRP "J_CLK" 15 nS                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 2.634ns    | 0    
   TO TIMEGRP "U_CLK" 15 nS                 |            |            |      
--------------------------------------------------------------------------------
  PATH "FROM U_CLK TO D_CLK"  TIG           | N/A        | N/A        | N/A  
--------------------------------------------------------------------------------
  PATH "FROM J_CLK TO D_CLK"  TIG           | N/A        | 13.950ns   | 6    
--------------------------------------------------------------------------------
  PATH "FROM D_CLK TO J_CLK"  TIG           | N/A        | 9.795ns    | 4    
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 21 secs 
Total CPU time to PAR completion: 20 secs 

Peak Memory Usage:  73 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file prescale_counter.ncd.


PAR done.