prescale_counter.npl

来自「FPGA-CPLD_DesignTool(example7）」· NPL 代码 · 共 31 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT prescale_counter
DESIGN prescale_counter
DEVFAM spartan2
DEVFAMTIME 1089196595
DEVICE xc2s200
DEVICETIME 1089196595
DEVPKG pq208
DEVPKGTIME 1089196595
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
STIMULUS testbench.tf
SOURCE prescale_counter.v
DEPASSOC prescale_counter prescale_counter.ucf
[Normal]
xilxBitgStart_Clk=xstvlg, spartan2, Verilog.t_bitFile, 1089197393, JTAG Clock
[STATUS-ALL]
prescale_counter.ncdFile=WARNINGS,1089364567
prescale_counter.ngdFile=WARNINGS,1089364553
[STRATEGY-LIST]
Normal=True