prescale_counter.pcf

FPGA-CPLD_DesignTool(example7）

"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_intcap/u_capstor/i_case1/i_rt0/u_ram/g_bram/1/u_bram/ram_rt0_s1_s4_if/ram_rt0_s1_s4_i/newSim2348.A"
;
PIN 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_intcap/u_capstor/i_case1/i_rt0/u_ram/g_bram/0/u_bram/ram_rt0_s1_s4_if/ram_rt0_s1_s4_i/newSim2352.A_pins<31>"
= NET "icon_control0<0>" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_intcap/u_capstor/i_case1/i_rt0/u_ram/g_bram/0/u_bram/ram_rt0_s1_s4_if/ram_rt0_s1_s4_i/newSim2352.A"
;
PIN 
"U_ila_pro_1/ila_pro_1/i_no_d/u_ila/i_intcap/u_capstor/i_case1/i_rt0/u_ram/g_bram/0/u_bram/ram_rt0_s1_s16_if/ram_rt0_s1_s16_i/newSim3134.A_pins<31>"
= NET "icon_control0<0>" BEL 
"U_ila_pro_1/ila_pro_1/i_no_d/u_ila/i_intcap/u_capstor/i_case1/i_rt0/u_ram/g_bram/0/u_bram/ram_rt0_s1_s16_if/ram_rt0_s1_s16_i/newSim3134.A"
;
TIMEGRP "J_CLK" = BEL "U_icon_pro/icon_pro/u_icon/u_tdi_reg" BEL 
"U_icon_pro/icon_pro/u_icon/u_tdo_reg" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/15/i_eq0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/14/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/13/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/12/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/11/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/10/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/9/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/8/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/7/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_cmd/g_target/6/i_ne0/u_target" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/6/i_eq0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/5/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/4/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/3/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/2/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/1/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/g_sync_word/0/i_ne0/u_fdr" BEL 
"U_icon_pro/icon_pro/u_icon/u_sync/u_sync" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/5/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/4/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/3/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/2/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/1/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_stat_cnt/g/0/u_fdre" BEL 
"U_icon_pro/icon_pro/u_icon/u_stat/u_tdo" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/8/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/7/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/6/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/5/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/4/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/3/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/2/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/1/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_count/g/0/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/i_srlt_eq_1/u_fd" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_rst/u_halt_xfer/u_tfdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_rst/u_arm_xfer/u_tfdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/1/u_m/u_mu/i_mut_gandx/u_match/i_tw_gte4/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/1/u_m/u_mu/i_mut_gandx/u_match/i_tw_gte4/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/2/u_m/u_mu/i_mut_gandx/u_match/i_tw_gte4/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tm/g_nmu/2/u_m/u_mu/i_mut_gandx/u_match/i_tw_gte4/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_srlt_eq_1/i_no_tseq/i_nmu_1_to_4/u_tcl/i_nmu_eq3/u_idout/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/31/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/30/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/29/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/28/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/27/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/26/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/25/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/24/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/23/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/22/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/21/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/20/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/19/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/18/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/17/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/16/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/15/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/14/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/13/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/12/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/11/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/10/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/9/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/8/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/7/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/6/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/5/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/4/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/3/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/2/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/1/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_cfg/u_cfg_fds/0/u_reg"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/s0_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/1/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/2/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/3/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/4/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/5/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/6/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/7/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/8/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/9/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/10/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/11/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/12/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/13/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/14/si_cfg/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_trig/u_tc/i_tseq_eq1/i_trig_simple/u_states/15/si_cfg/i_srl_t1/u_srl16e"
BEL "U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/8/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/7/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/6/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/5/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/4/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/3/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/2/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/1/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_stat_cnt/g/0/u_fdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_dsl1/u_tfdre" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_dirty" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_reset_edge/u_dout0" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_reset_edge/u_dout1" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_reset_edge/i_h2l/u_dout" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_stat/u_tdo" BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/0/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/1/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/2/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/3/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/4/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/5/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/6/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/7/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/8/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/9/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/10/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/11/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/12/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/13/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/14/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/15/u_sel"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/i_0_to_64k/i_srl/u_selx"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_scnt_cmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_scnt_cmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_scnt_cmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_scnt_cmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/i_tw_gte8/f_tw/0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srlh"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/i_twmod8_ne0/i_no_rpm/i_srlt_eq_1/u_srll"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/i_srlt_eq_1/u_ns1/i_srl_t1/ug_cfglut5/i_srl_t1/ug_cfglut4/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/i_srlt_eq_1/u_ns1/i_srl_t1/ug_cfglut5/i_srl_t1/uf_cfglut4/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/i_srlt_eq_1/u_ns1/i_srl_t1/uf_cfglut5/i_srl_t1/ug_cfglut4/i_srl_t1/u_srl16e"
BEL 
"U_ila_pro_0/ila_pro_0/i_no_d/u_ila/u_capctrl/i_srlt_eq_1/u_ns1/i_srl_t1/uf_cfglut5/i_srl_t1/uf_cfglut4/i_srl_t1/u_srl16e"