prescale_counter.cdc

FPGA-CPLD_DesignTool(example7）

#ChipScope Core Inserter Project File Version 3.0
#Fri Jul 09 17:15:43 CST 2004
Project.device.designInputFile=D\:\\My_Design\\Example-7-3\\chipscope_Demo\\prescale_counter\\prescale_counter.ngc
Project.device.designOutputFile=D\:\\My_Design\\Example-7-3\\chipscope_Demo\\prescale_counter\\prescale_counter.ngc
Project.device.deviceFamily=4
Project.device.enableRPMs=true
Project.device.outputDirectory=D\:\\My_Design\\Example-7-3\\chipscope_Demo\\prescale_counter\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=1
Project.filter<0>=
Project.icon.boundaryScanChain=0
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=2
Project.unit<0>.clockChannel=clk_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=16
Project.unit<0>.enableGaps=false
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=counter_0
Project.unit<0>.triggerChannel<0><1>=counter_1
Project.unit<0>.triggerChannel<1><0>=counter_2
Project.unit<0>.triggerChannel<1><1>=counter_3
Project.unit<0>.triggerChannel<1><2>=counter_4
Project.unit<0>.triggerChannel<1><3>=counter_5
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=2
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<1><1>=0
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<1><1>=1
Project.unit<0>.triggerPortCount=2
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=2
Project.unit<0>.triggerPortWidth<1>=4
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
Project.unit<1>.clockChannel=clk_BUFGP
Project.unit<1>.clockEdge=Rising
Project.unit<1>.dataDepth=256
Project.unit<1>.dataEqualsTrigger=true
Project.unit<1>.dataPortWidth=16
Project.unit<1>.enableGaps=false
Project.unit<1>.enableTimestamps=false
Project.unit<1>.timestampDepth=0
Project.unit<1>.timestampWidth=0
Project.unit<1>.triggerChannel<0><0>=counter_8
Project.unit<1>.triggerChannel<0><1>=counter_9
Project.unit<1>.triggerChannel<0><2>=counter_10
Project.unit<1>.triggerChannel<0><3>=counter_11
Project.unit<1>.triggerChannel<0><4>=counter_12
Project.unit<1>.triggerChannel<0><5>=counter_13
Project.unit<1>.triggerChannel<0><6>=counter_14
Project.unit<1>.triggerChannel<0><7>=counter_15
Project.unit<1>.triggerConditionCountWidth=0
Project.unit<1>.triggerMatchCount<0>=1
Project.unit<1>.triggerMatchCountWidth<0><0>=0
Project.unit<1>.triggerMatchType<0><0>=0
Project.unit<1>.triggerPortCount=1
Project.unit<1>.triggerPortIsData<0>=true
Project.unit<1>.triggerPortWidth<0>=8
Project.unit<1>.triggerSequencerLevels=16
Project.unit<1>.triggerSequencerType=1
Project.unit<1>.type=ilapro