📄 startup.s
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AREA Init, CODE, READONLY, ALIGN=5
; HEADER FILES
;
INCLUDE common.inc
INCLUDE startup.inc
INCLUDE gpioInit.mac
INCLUDE platform.mac
INCLUDE intInit.mac
INCLUDE ostInit.mac
INCLUDE cp15.mac
INCLUDE clockinit.mac
INCLUDE rtcInit.mac
INCLUDE memInit.mac
INCLUDE cp14.mac
INCLUDE ChangeFreq.mac
EXPORT BlinkLed
EXPORT IRQ_Handler
EXPORT Exceptions
IMPORT CEntry ; "C" platform main entrypoint
;
; The following symbols control various features of the low-level
; initialization code.
;
;
; References to external symbols
;
;
; Public routines
;
;
; Main entry point
;
ENTRY
;
; Exception vectors
;
Vectortable
b Reset_Handler ; Must be PIC
Exceptions
ldr pc, Undefined_Handler_addr
ldr pc, SWI_Handler_addr
ldr pc, Prefetch_Handler_addr
ldr pc, Abort_Handler_addr
nop
ldr pc, IRQ_Handler_addr
ldr pc, FIQ_Handler_addr
VectortableEnd
Undefined_Handler_addr
DCD Undefined_Handler - Vectortable
SWI_Handler_addr
DCD SWI_Handler - Vectortable
Prefetch_Handler_addr
DCD Prefetch_Handler - Vectortable
Abort_Handler_addr
DCD Abort_Handler - Vectortable
IRQ_Handler_addr
DCD IRQ_Handler - Vectortable
FIQ_Handler_addr
DCD FIQ_Handler - Vectortable
;
; The RESET entry point
;
Reset_Handler
;
; Put the processor into SVC mode with interrupts disabled (IRQ and FIQ).
;
mrs r14,CPSR ; get the processor status
bic r14,r14,#CPSR_Mode_Mask
orr r14,r14,#(CPSR_Mode_SVC:OR:CPSR_Int_Mask)
msr cpsr_cf,r14 ; SVC 32 mode with interrupts disabled
initGpio r0,r1,r2
; initPlatform r2,r3
; initReset r0, r1, r2
initIntCntrlr r2, r3
initOST r6, r7 ;enable OIER bit OIER_E1, but there are issues in this macro
enableICacheBtb r0
initClocks r2, r3
initRTC r0,r1
initPower r0, r1, r2
isMmuEnabled r0
;beq %F01
getARMControl r0
bic r0,r0,#0x4 ;Disable D-Cache
bic r0,r0,#0x800 ;Disable BTB
bic r0,r0,#0x1 ;Disable MMU
setARMControl r0
getAuxControl r0
orr r0,r0,#0x1 ;Disable Write Buffer
setAuxControl r0
;initMemCntrlr r2, r3, r6, r7
01
;change core frequency according to the hexswitch value
changeFreq r0, r1, r2
; restartMemCntrlr r0, r2, r3
getARMControl r0
bic r0,r0,#0x4 ;Disable D-Cache
; bic r0,r0,#0x1000 ;Disable I-Cache
bic r0,r0,#0x800 ;Disable BTB
bic r0,r0,#0x1 ;Disable MMU
setARMControl r0
getAuxControl r0
orr r0,r0,#0x1 ;Disable Write Buffer
setAuxControl r0
b %F02
LTORG
02 nop
; IF RELOCATE_ROM = 1
; bl CopyROM
; bl StartAtRAM
; ENDIF ; RELOCATE_ROM
;
; Get the top of the RAM we can use for stack space.
;
ldr r0, =STACK_LOCATION
mov r10, r0 ; Save the top of memory
;
; Now setup the stack.
;
; Enter SYS mode and set up the SYS stack pointer
;
mov r1, #CPSR_Mode_SYS:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter UND mode and set up the UND stack pointer
;
mov r1, #0x1b:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter ABT mode and set up the ABT stack pointer
;
mov r1, #0x17:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter FIQ mode and set up the FIQ stack pointer
;
mov r1, #CPSR_Mode_FIQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter IRQ mode and set up the IRQ stack pointer
;
mov r1, #CPSR_Mode_IRQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Set up the SVC stack pointer last and return to SVC mode
;
mov r1, #CPSR_Mode_SVC:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
ldr r9, =RAM_Base
; swi 0
bl CEntry
; mov pc,#0 ;restart
210
onCPLD_LED0 r1, r2
pauseMilliSecs #250, r1, r2, r3
offCPLD_LED0 r1, r2
pauseMilliSecs #500, r1, r2, r3
b %B210
;------------------------------------------------------------------------------
;
; FUNCTION:
; CopyROM
;
; DESCRIPTION:
; This routine relocates the POST to SDRAM.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; None.
;
; GLOBAL EFFECTS:
; The contents of POST stored in Flash is copied to SDRAM.
;
; ASSUMPTIONS:
; The memory controller has been initialized.
;
; CALLS:
; None.
;
; CALLED BY:
; POST.
;
; PROTOTYPE:
; VOID CopyROM(VOID);
;
;------------------------------------------------------------------------------
;
; Copy the ROM image to RAM and prepare for remap
;
CopyROM
;
; Now setup the registers as follows:
; R1 = Destination Address
; R2 = Source Starting Address
; R3 = Source Ending Address
;
ldr r1, =RAM_Source_Base ; Destination Address
ldr r2, =ROM_Base ; Source Starting Address
ldr r3, =ROM_Size ; Size of Source
add r3, r3, r2 ; Calculate Source Ending Address
;
; Copy Source to Destination
;
100 ldr r0,[r2],#4
str r0,[r1],#4
;
; Check for end of copy
;
cmp r2,r3
bls %B100
;
; Verify the copy, setup the registers as follows:
; R1 = Destination Address
; R2 = Source Starting Address
; R3 = Source Ending Address
;
ldr r1, =RAM_Source_Base ; Destination Address
ldr r2, =ROM_Base ; Source Starting Address
;
; Verify that source equals destination
;
200 ldr r0,[r2],#4
ldr r4,[r1],#4
cmp r0,r4
bne CopyFail
;
; Check for end if verify
;
cmp r2,r3
bls %B200
mov pc,lr
CopyFail
210
onCPLD_LED1 r1, r2
pauseMilliSecs #500, r1, r2, r3
offCPLD_LED1 r1, r2
pauseMilliSecs #500, r1, r2, r3
b %B210
;------------------------------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
; FUNCTION:
; StartAtRAM
;
; DESCRIPTION:
; This routine determines the address in RAM we should jump to.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; None.
;
; GLOBAL EFFECTS:
; Once this routine is executed, we're running from RAM.
;
; ASSUMPTIONS:
; The POST has been copied from Flash to RAM.
;
; CALLS:
; None.
;
; CALLED BY:
; POST.
;
; PROTOTYPE:
; VOID StartAtRAM(VOID);
;
;------------------------------------------------------------------------------
;
; Jump to the same address in RAM. Nothing to do in particular
; here because we are jumping back to the same address, just executing from
; RAM. At this point we are running from ROM that has been remapped to ROM_BASE.
StartAtRAM
;
; Calculate the new address in RAM by taking the current address and subtract
; ROM_BASE. On return, we should be running from RAM.
;
ldr r0, =RAM_Source_Base ; Get Destination Address
add pc,lr,r0 ; Back plus our load offset
;------------------------------------------------------------------------------
BlinkLed
; get the gpio register block base address
ldr r3, =GPIOREGS_PHYSICAL_BASE
;modified by maple 2002/8/17
ldr r2, =0x08100000
;modified by maple 2002/8/17
; get the pin values for GPDRx
ldr r0, [r3, #GPDRx_OFFSET]
orr r0,r0,r2
str r0, [r3, #GPDRx_OFFSET]
903
str r2, [r3, #GPCRx_OFFSET]
ldr r1, =16000000
901 subs r1, r1, #1
bne %B901
str r2, [r3, #GPSRx_OFFSET]
ldr r1, =16000000
902 subs r1, r1, #1
bne %B902
b %B903
mov pc,lr
;---------------------------------
; unsigned int GetMMUConf(void)
; return value: cp15 reg1, control register
;---------------------------------
GetMMUConf
stmfd sp!,{r1-r12,lr}
getARMControl r0
ldmfd sp!,{r1-r12,lr}
mov pc,lr
;---------------------------------
; int EnableIrq(void)
; return cpsr
;---------------------------------
EnableIrq
mrs r0, cpsr
bic r0, r0, #CPSR_I_Bit
;bic r0, r0, #CPSR_F_Bit
msr cpsr_c, r0
mov pc,lr
Undefined_Handler
bl BlinkLed
SWI_Handler
bl BlinkLed
Prefetch_Handler
bl BlinkLed
Abort_Handler
bl BlinkLed
IRQ_Handler
bl BlinkLed
FIQ_Handler
bl BlinkLed
END
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