syslib.c

WINDRIVER MCP750 BSP

/* sysLib.c - Motorola MCPX750 board series system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
02t,21jun02,mil  Updated sysSmAnchorFind().
02s,29apr02,mil  Updated shared memory macros and sysSmAnchorFind().
02r,01nov01,mil  Cleaned up compiler warnings.
02q,16oct01,mil  Fixed boot hanging in sysHawkMsDelay(), needed besides
                 removing asm bclr (SPR 27046).
02p,15dec99,rhv  Added support for non-MCPN750 cPCI boards.
02o,21nov99,tm   Updated mcp750 END support to more easily support components
02n,01jun99,srr  Supplemented sysSmParamsCompute with sysSmArg2Compute.
02m,17may99,tm   Replaced BSP call sysGetDec with PPC arch routine vxDecGet
02l,10may99,srr  Replaced sysPciNextClass with pciFindDevice in
                 sysDec2155xPriIntConnect.  Remove call to pciScanlistCreate.
02k,20apr99,srr  Changed file name and routine references to dec21x40.
02j,20apr99,srr  Replaced sysPciNextClass with pciFindClass in sysDynEnetFind.
02i,20apr99,srr  Removed sysPciConfigInsertLong, sysPciConfigInsertWord, &
                 sysPciConfigInsertByte.
02h,19apr99,srr  Removed sysDynDcAttach. 
02g,19apr99,srr  added GUARDED attributes to non-local memory areas mapped in
		 sysPhysMemDesc[]. (SPR 23674)
02f,15apr99,srr  Changed to WRS address space naming convention.
02e,09apr99,srr  Changed vpdShow.c to sysMotVpdShow.c
02d,23mar99,scb  sysSmParamsCompute() computes value for byte-long smIntArg2
02c,26feb99,scb  sysSmAnchorFind() uses PCI_SYSTEM_DRAM_ADRS, 
		    not PCI2DRAM_BASE_ADRS
02b,22feb99,scb  Minor commentary cleanup.
02a,27jan99,scb  Code cleanup involving INCLUDE_SCSI.
01z,27jan99,scb  Changed sysDec21x40UpdateLoadStr to sysDec21x4xUpdateLoadStr
01y,26jan99,scb  Removed references to SECONDARY_ENET.
01x,25jan99,scb  Replaced ROM_BASED with PCI_AUTOCONFIG_DONE macro.
01w,18jan99,scb  Added support for END driver on dec21143.
01v,02dec98,scb  Minor comment modification for sysSmAnchorFind().
01u,18nov98,scb  Add test to configure PCI busses only on ROM startup.
01t,13nov98,rhv  Modified sysLocalToBusAdrs() and sysBusToLocalAdrs() for
		 use with both local and Compact PCI bus addresses. Also did
		 some formatting clean-up.
01s,11nov98,scb  Modified to not reconfigure PCI busses if already configured
01r,05nov98,scb  Add shared memory support for nonhost node zero.
01q,04nov98,rhv  Fixed a bug in sysDec2155xPriIntConnect().
01p,28oct98,rhv  Added sysPciOutByte/Word/LongConfirm() routines for use where
		 PCI posting buffers must be flushed after the write. Also
		 added PCI posted write buffer flushes to sysDec2155xIntr() to
		 prevent possible slow interrupt clearing and spurious MPIC
		 interrupts.
01o,19oct98,rhv  Fixing a bug in sysPciInsertWord.
01n,21sep98,rhv  Added VPD support and correct sequence error in file
		 modification history.
01m,08sep98,rhv  Added cPCI Bus Probe support and simplified the general
		 PCI bus probe mechanism to eliminate the need for a
		 machine check.
01l,04sep98,scb  Added shared memory support (MCP750 master and mem repository)
01k,28aug98,rhv  Adding support for processor data bus parity and
		 fixing bugs in sysPciInsertLong, Word and Byte.
01j,05aug98,rhv  Re-formating Raven window offset arrays plus some minor
		 comment clean-up.
01i,29jul98,rhv  Added Dec2155x support routines and changed sysBusToLocalAdrs
		 and sysLocalToBusAdrs.
01h,21jul98,scb  #define cleanup, narrow support to just MCP750, MCPN750.
01g,16jul98,scb  Interrupt support for MCPN750, some cleanup.
01f,07jul98,scb  Initial support for MCPN750.
01i,05jun98,mas  removed the includes of ataDrv.h, pccardLib.h, and ataDrv.c;
		 changed return type of sysIntEnablePIC() from void to STATUS;
		 updated chip driver list (SPR 21482).
01h,02jun98,mas  reversion to Motorola code for PCI auto config.
01g,21may98,mas  merged mcp750 and mtx603 code; fixed legacy bug (SPR 21271).
01f,18may98,dat  added inclusion of pciConfigShow.c, SPR 21213
01e,16apr98,db	 added floppy disk support, removed #if FALSE from around
		 sysLanIntDisable()
01d,06apr98,rhk  switched over to use pciConfigLib.
01c,02apr98,dat  added sysDelay, chg declarations for sysInXxx functions
01b,15jan98,srr changed auxiliary clock for MCP750 to use Raven timer.
01a,09jan98,rhk  created (from version 02d, mv2600/sysLib.c).
*/

/*
DESCRIPTION
This library provides board-specific routines.	The chip drivers included are:

    i8250Sio.c		- Intel 8250 UART driver
    ppcDecTimer.c	- PowerPC decrementer timer library (system clock)
    ravenAuxClk.c	- Motorola Raven timer driver for auxiliary clock.
    ravenMpic.c		- raven Mpic / W83C553 PIB/IBC Interrupt Controller
    ravenPci.c		- Raven PCI Bus bridge chip initialization
    pciAutoConfigLib.c	- PCI device auto-configuration library
    pciConfigLib.c	- PCI Configuration Space Access Library
    pciConfigShow.c	- Show routines of PCI bus library.
    dec21x40End.o	- 10baseT/100baseTX DEC 21x4x Ethernet driver
    byteNvRam.c 	- byte-oriented generic non-volatile RAM library
    ns8730xSuperIo.c	- Super I/O chip initialization
    ataDrv.o		- ATA/EIDE interface driver
    isaDma.c		- I8237 ISA DMA transfer interface library
    fdcDrv.c		- driver for PS2 floppy device controller(FDC)
    dec2155xCpci.c	- DEC 2155x Non-Transparent PCI-to-PCI Bridge support.
    sysMotVpd.c		- Motorola Vital Product Data Support.
    hawkI2c.c 		- Falcon/Hawk I2C support.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/end/dec21x40End.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "./dec2155xCpci.h"
#ifdef INCLUDE_SM_COMMON
#   include "smLib.h"
#   include "smUtilLib.h"
#   include "smPktLib.h"
#   include "smObjLib.h"
#endif  /* INCLUDE_SM_COMMON */

#ifdef INCLUDE_FD
#   include "fdcDrv.c"		/* include floppy disk driver */
#   include "isaDma.c"		/* include DMA driver */
#endif

/* defines */

#define ZERO	0

#define DEFAULT_TAS_CHECKS	10		/* rechecks for soft tas */
#define TAS_CONST		0x80

#ifdef INCLUDE_DPE
#   define _PPC_HID0_DBP _PPC_HID0_ECPC
#   define FALCON_ADDR( reg ) ( FALCON_BASE_ADRS + reg )
#   define RAVEN_MIN_DPE_REV 5 /* min rev that supports proc data bus parity */
#endif /* INCLUDE_DPE */

#define RAVEN_ADDR( reg )	( RAVEN_BASE_ADRS + reg )
#define RAVEN_RDWR_ENA		(CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN)

#define RAVEN_ERR_STS_MSK (RAVEN_MPC_MEREN_RTAI | \
			   RAVEN_MPC_MEREN_SMAI | \
			   RAVEN_MPC_MEREN_SERRI)

#define RAVEN_ERR_DIS (RAVEN_MPC_MEREN_RTAI | \
		       RAVEN_MPC_MEREN_SMAI | \
		       RAVEN_MPC_MEREN_SERRI | \
		       RAVEN_MPC_MEREN_RTAM | \
		       RAVEN_MPC_MEREN_SMAM | \
		       RAVEN_MPC_MEREN_SERRM)

/* structures */

typedef struct ravenWinStruct
    {
    UINT32 winType;   /* mem or i/o */
    UINT32 winBase;   /* start of window */
    UINT32 winLimit;  /* end of window */
    } RAVEN_WIN_STRUCT;

typedef struct ravenOffsets
    {
    UINT32 range;
    UINT32 offset;
    UINT32 attr;
    } RAVEN_OFFSETS;

RAVEN_OFFSETS	sysRavCpuWinOff [] =
    {

	{
	RAVEN_ADDR(RAVEN_MPC_MSADD0),
	RAVEN_ADDR(RAVEN_MPC_MSOFF0),
	RAVEN_ADDR(RAVEN_MPC_MSATT0)
	},

	{
	RAVEN_ADDR(RAVEN_MPC_MSADD1),
	RAVEN_ADDR(RAVEN_MPC_MSOFF1),
	RAVEN_ADDR(RAVEN_MPC_MSATT1)
	},

	{
	RAVEN_ADDR(RAVEN_MPC_MSADD2),
	RAVEN_ADDR(RAVEN_MPC_MSOFF2),
	RAVEN_ADDR(RAVEN_MPC_MSATT2)
	},

	{
	RAVEN_ADDR(RAVEN_MPC_MSADD3),
	RAVEN_ADDR(RAVEN_MPC_MSOFF3),
	RAVEN_ADDR(RAVEN_MPC_MSATT3)
	}

    };

RAVEN_OFFSETS	sysRavPciWinOff [] =
    {

    {PCI_CFG_RAVEN_PSADD0, PCI_CFG_RAVEN_PSOFF0, PCI_CFG_RAVEN_PSATT0},
    {PCI_CFG_RAVEN_PSADD1, PCI_CFG_RAVEN_PSOFF1, PCI_CFG_RAVEN_PSATT1},
    {PCI_CFG_RAVEN_PSADD2, PCI_CFG_RAVEN_PSOFF2, PCI_CFG_RAVEN_PSATT2},
    {PCI_CFG_RAVEN_PSADD3, PCI_CFG_RAVEN_PSOFF3, PCI_CFG_RAVEN_PSATT3}

    };

#define RAVEN_CPU_WIN_CNT (sizeof (sysRavCpuWinOff)/ sizeof (RAVEN_OFFSETS))
#define RAVEN_PCI_WIN_CNT (sizeof (sysRavPciWinOff)/ sizeof (RAVEN_OFFSETS))
#define RAVEN_WIN_CNT (RAVEN_CPU_WIN_CNT + RAVEN_PCI_WIN_CNT)

#ifdef DEC2155X_SYSTEM_SUPPORT

typedef struct dec2155xCpci
    {
    UINT32 intLine;
    UINT32 csrAddr;
    } DEC2155X_CPCI;

DEC2155X_CPCI	dec2155xCsrInfo[MAX_SM_DEVICE_COUNT];
UINT		dec2155xLastCsr;

#endif

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.	User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers can be disabled if the VS and VP bits are both clear
 * in the upper BAT register of each pair.  In the default configuration
 * (coded below) the VS and VP bits are cleared and thus the BAT registers
 * are disabled.  To enable the BAT registers, change the construct coded
 * below the upper BAT register:
 *
 *	      & ~(_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which clears VS and VP
 *				to
 *	      | (_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which sets VS and VP
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *	  8 Meg 		     64 K
 *	 16 Meg 		    128 K
 *	 32 Meg 		    256 K
 *	 64 Meg 		    512 K
 *	128 Meg 		      1 Meg
 *	.				.
 *	.				.
 *	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 * *** EXTENDED_VME configuration ***
 *
 * The user can use TLBs, and/or BATs, to map VME A32 space to the processor.
 * The default is to use TLBs (MMU).  Change the table entry below to use
 * a different method. (See "MODIFY A32 VME WINDOW HERE")
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Local DRAM - Must be second entry in sysPhysMemDesc for Auto Sizing */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI ISA memory space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI memory space */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* MPIC Regs */

    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FALCON_BASE_ADRS,
    (void *) FALCON_BASE_ADRS,
    FALCON_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) RAVEN_BASE_ADRS,
    (void *) RAVEN_BASE_ADRS,
    RAVEN_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,