target.nr

WINDRIVER MCP750 BSP

The other two serial ports are serial ports 3 and 4.  All but the DTR and
DSR lines for these ports are implemented in the Zilog Z85230 ESCC chip.
The DTR and DSR lines for serial ports 3 and 4 are implemented in the
Zilog Z8536 CIO chip.  Serial ports 3 and 4 can be configured as
synchronous serial ports but no support for this mode is provided by this BSP.

By default, all serial ports are configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware 
handshake.  Hardware handshake using RTS/CTS is a supported option on all ports.

The MCP750 transition module has two RJ-45 connectors for COM1 and COM2;
these are permanently configured as DTE.  Serial ports 3 and 4 have
special HD-26 connectors and require Serial Interface Modules (SIMs) that come
configured as DCE or DTE versions of EIA-232, EIA-530, X.21 or V.35.  
For details, consult 
\f2TMCP 700 Transition Module Installation and Use\f1.

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX
compatible.  

The MCP750 uses an RJ45 (twisted pair)
jack and can be used with either 10baseT or 100baseTX.  The Ethernet driver
automatically senses and configures the port as 10baseT or 100baseTX.  The
Ethernet driver is compatible with DEC21040, DEC21140, and DEC21143 devices.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21140 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM at offset 0x202c.

.SS "Compact Flash Configuration"
Compact Flash is supported on the MCP750 as IDE controller 0, device 0.  To
configure the compact flash, perform the following:
.IP "1)"
In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
.IP "2)"
Make sure that the ATA_DEV0_STATE line reads:

.CS
        #define ATA_DEV0_STATE DEV_PRESENT
.CE
.IP "3)"
Rebuild the kernel.  After booting, the compact flash device can
be configured with the following command:

.CS
        usrAtaConfig(0,0,"/ata0")
.CE

.SS "Floppy Disk Configuration"
A PC-compatible floppy disk is supported on the MCP750 via a PS/2 connector
on the TMCP700 transition module.  To configure the floppy disk, perform the
following:
.IP "1)"
In config.h, replace "#undef INCLUDE_FD" with "#define INCLUDE_FD".
.IP "2)"
If a DOS file system is needed, #define INCLUDE_DOSFS in config.h.
.IP "3)"
Rebuild the kernel.  After booting, the floppy disk can be accessed as a raw
device and/or a DOS file system disk if INCLUDE_DOSFS was defined.

Refer to the \f2VxWorks Programmer's Guide, section 4.2\f1 for
information on the DOS file system, its configuration, and use.

.SS "Universal Serial Bus Configuration"
Two USB ports are supported on the MCP750.  They are located on the front
panel as J17 and J18, and can be re-routed to the optional transition
module TMCP700.  The USB controller is inside the PCI Peripheral Bus
Controller (PBC) on the MCP750 and is HCI v1.1 compatible.

The \f2USB Developer Kit\f1 for Tornado is available as an optional product.
It includes a USB stack for VxWorks, as well as drivers for various types
of USB peripherals.  Detailed information can be obtained from the
\f2USB Developer Kit\f1 documentation.  

To enable PCI auto configuration of the USB device, the file sysBusPci.c
needs to be modified.  In sysPciAutoConfigInclude(), the \f3case PCI_ID_USB\f1
in \f3switch(devVend)\f1 should be changed to return OK instead of ERROR.
After this change, rebuild and flash a new bootrom by following the
instructions in the "ROM Considerations" section.  After verifying the new
bootrom is functioning properly, proceed to the \f2USB Developer Kit\f1
documentation.

.SS "Boot Devices"
The supported boot device is:

    \f3dc\f1 - Ethernet (10baseT or 100baseTX or AUI)

Motorola's PPC1-Bug can be used to download and run VxWorks.
Consult the user's manuals for details.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

.SS "ROM Considerations"
Use the following command sequence on the host to re-make the BSP boot ROM:
.CS    
    cd target/config/mcp750
    make clean
    make bootrom.bin
    chmod 666 bootrom.bin
    cp bootrom.bin /tftpboot/bootrom.bin
.CE

Power down the board and switch the ROM jumper to select socketed FLASH.
Connect the Ethernet and console serial port cables, then power the board back
up.

.SS "Flashing the Boot ROM Using Motorola PPC1-Bug:" 1

At the PPC1-Bug prompt, set up the network transfer from a TFTP host using 
`niot'.  Important: You must have a TFTP server running on your host's
subnet for the `niop' command to succeed.  Using `niot', the Client IP Address,
Server IP Address, and Gateway IP Address must be set up for the user's
specific environment:

.CS
   PPC1-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC1-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  The file name must be set to the location
of the binary file on the TFTP host.  The binary file must be stored
in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC1-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? bootrom.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC1-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into soldered FLASH parts.

.CS
   PPC1-Bug>pflash 4000:FFF00 ff000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select soldered FLASH.  Then power the board back up.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

.SS "Delivered Objects"
The delivered objects are: `bootrom', `bootrom.hex', `vxWorks', 
`vxWorks.sym', and `vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name, or `.bin' to each to derive a
binary format file name.

.ne 9
.nf
`bootrom'
`bootrom_uncmp'
`bootrom_res_high'
`vxWorks' (with `vxWorks.sym')
`vxWorks.st'
`vxWorks_rom'
`vxWorks.st_rom'
`vxWorks.res_rom_res_low' (builds but does not execute)
`vxWorks.res_rom_nosym_res_low' (builds but does not execute)
.fi

Note, "bootrom_res", "vxWorks.res_rom", and "vxWorks.res_rom_nosym" are
also make targets but are not part of the PowerPC supported set.  These
particular targets will not build in the PowerPC environment.

.SS "Special Routines"
For these boards, the value of the CPU clock speed is read from the CPU 
configuration register using the macro MEMORY_BUS_SPEED which is defined
in mcpx750.h.  For example:

.CS
   clkFreqMhz = MEMORY_BUS_SPEED;
.CE

.SS "Known Problems"

MCP750 boards prior to REV D have a hardware problem in which ISA
interrupts which are supposed to be level sensitive do not function
properly.  The software automatically detects such boards and
configures the ISA interrupts for edge sensitivity instead of level
sensitivity.  This allows the serial ports to function on pre-REV D
boards.  A side effect of the problem however, is that that a serial
port, under a heavy load, may hang due to a missed interrupt.  Boards
which are REV D and later have had their hardware modified to allow
the ISA interrupts to properly function in level mode and the software
will detect this and perform the necessary programming to respond to
level sensitive interrupts.  REV D and later boards will not
experience serial port hangs due to edge/level sensitivity problems.

To determine if the board is REV D or later, refer to the circuit board
number which is printed on the back side of the board, near the front
panel USB 0 port opening.  The number is etched into the copper.
A number such as "01-W3288F01C" will appear.  The last character ("C"
in this example) will indicate the revision level.

.IP "1)"
The serial port (console) appears to work fine, but it does lock up while
running the Wind River Validation Test Suite.

.IP "2)"
The routine ataShow does not display the information for the secondary ATA
controller when devices are attached to it.  The devices function properly
though, it is just the ataShow routine that has problems.

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address map. Tornado-compatible mapping deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start (CPU addr)	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x80000000 - LOCAL_MEM_SIZE)	[Not used]
0x80000000	64K	PCI I/O space (16-bit)
0x80010000	8M-64K	[Not Used]	
0x80800000	8M	Direct Map PCI Cfg. Space
0x81000000	1G-16M (0x3F000000)	PCI I/O space (32-bit)
0xC0000000	1G-48M (0x3D000000)	PCI MEM space
0xFD000000	504M (0x1F800000)	Reserved
0xFEF80000	64K	Falcon Registers
0xFEF90000	384K	Reserved
0xFEFF0000	64K	Raven Registers
0xFF000000	8M	ROM/FLASH Bank A
0xFF800000	1M	ROM/FLASH Bank B
0xFF900000	6M	Reserved
0xFFF00000	1M	ROM/FLASH Bank A or Bank B
.TE

.SH "BOARD LAYOUT"
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks
configuration:

Serial ports 1 and 2, the Ethernet port, and the two USB ports appear both
on the MCP750 and the TMCP700-001 transition module.  The parallel port,
serial ports 3 and 4, and the keyboard/mouse port appear only on the
TMCP700-001 transition module.

.ne 4i

.bS
____________________________________________________________________________
|                          Needs TMCP700-001                               |
|                          Transition Module                               |
____________________________________________________________________________
|                           ...............................................|
|  ========== ==========    .                                             .|
|                           . ============== (Compact Flash)              .|
|  ========== ==========    .                                             .|
|         PMC slot          .                                             .|
|                           .                                             .|
|                           . RAM300 DRAM mezzanine board                 .|
|                           .                               ...............|
|                           .                               .              |
|                           .                               .              |
|                           .                               .              |
|                           .                               .              |
|                           .       +----+                  .              |
|                           .       |    |<== (PPC1Bug)     .              |
|                           .       |    |                  .              |
|                           .       +----+                  .              |
|                           .        (XU1)                  .              |
|                           .         +----+                .              |
|D J6                       .         |    |                .              |
|                           .         |    |                .              |
|                           .         +----+                .              |
|                           .          (XU2)                .              |
|                           .                               .              |
|                           .................................              |
|__........................___----____----_______________________---__---__|
                             10/100   Com1                       USB  USB
                             Base T                               1    2
.bE
    Key: 
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    () Features labeled in parentheses are below the mezzanine board.

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "MCP 750 CompactPCI Single Board Computer Installation and Use,"
.iB "TMCP 700 Transition Module Installation and Use,"
.iB "Motorola MPC750 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "VT82C586B PCI Peripheral Bus Controller,"
.iB "DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "PC87307VUL Super I/O Device Data Manual,"
.iB "Zilog SCC (Serial Communications Controller) User's Manual,"
.iB "Zilog ZCIO Counter/Timer and Parallel I/O Unit User's Manual,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "PICMG 2.0 D2.14 CompactPCI Specification,"
.iB "IEEE Standard 1284 Bidirectional Parallel Port Interface Specification,"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"
.iB "IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC),"
.iB "SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet."