target.nr

WINDRIVER MCP750 BSP

'\" t
.so wrs.an
.\" PowerPlus/target.nr - Motorola PowerPlus target-specific documentation
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.\" Copyright 1984-2001 Wind River Systems, Inc.
.\" Copyright 1996,1997,1998,1999 Motorola, Inc., All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01a,30apr02,mil  Changed SYS_CPCI_BUS_NUMBER to SYS_SM_CPCI_BUS_NUMBER.
.\" 02d,29nov01,mil  Changed USB ports to supported and added USB information.
.\" 02c,24aug01,dgp  change manual entry to reference entry per SPR 23698
.\" 02b,15dec99,rhv  Adding support for non-MCPN750 boards.
.\" 02a,25feb99,scb  Writeup on SENS support.
.\" 01z,08feb99,scb  Clarification in "Make Targets" section.
.\" 01y,01dec98,scb  One-line tweek about SM_ANCHOR_OFFSET value.
.\" 01x,23nov98,scb  Readded "Added address translation information" which was
.\"                  accidently dropped from 2.2 version.
.\" 01v,18nov98,scb  Added "PCI autoconfiguration roll call" information.
.\" 01u,16nov98,scb  Added Shared Memory Support information.
.\" 01t,05jun98,mas  updated Known Problems for board revisions (SPR 21482).
.\" 01s,29may98,mas  updated driver list and bootrom make instructions.
.\" 01r,29may98,mas  added Compact Flash and floppy disk configuration info;
.\"		     updated supported/unsupported lists of peripherals, driver
.\"		     list, and board layout.
.\" 01q,23apr98,scb  corrected error in interrupt vector assignment description.
.\" 01p,13jan98,scb  cloned MCP750 version from mv2700 version.
.\" 01o,21oct97,scb  cloned mv2700 version from mv2604 version.
.\" 01n,10oct97,srr  change name from NexGen to PowerPlus.
.\" 01m,27aug97,dgp  doc: final editing
.\" 01l,13aug97,mas  split into seperate files for each board family.
.\" 01k,24jul97,mas  added VME interrupt info and guidelines; added MPIC
.\"		     priority scheme (SPR 8956).
.\" 01j,17jul97,mas  added dynamic memory sizing info (SPR 8824).
.\" 01i,09jul97,mas  added serial ports 3 & 4 (SPR 8566) and PPC1-Bug flash ROM 
.\"                  info.  Rewritten to meet new guidelines.
.\" 01h,30apr97,mas  added extended VME, mv360x and mv230x info (SPR 8410).
.\" 01g,02apr97,dat  added VME config info, SPR 8271, fixed model nbr table
.\" 01f,05mar97,mas  changed GET_CPU_SPEED to MEMORY_BUS_SPEED; deleted ref to
.\"		     CPU_SPEED_MHZ; added tftp server required to burn flash
.\"		     (SPR 8114).
.\" 01e,18feb97,mas  clarified use of transition modules and board diagram
.\"                  (SPR 7772, 7811, 7832).
.\" 01d,10jan97,dat  cleaned up flash loading documentation
.\"             mas
.\" 01c,02jan97,wlf  doc: cleanup.
.\" 01b,01jan97,dat  added mod history
.\" 01a,01sep96,mot  written (Motorola Comp. Grp)
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.\"
.TH "MCP750" T "Motorola PowerPlus" "Rev: 13 Jan 98" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MCP750"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

The Motorola PowerPlus series of boards consists of the following families: 
MVME230x, MVME260x, MVME360x, MVME2700, MTX60x, and MCP750.  This BSP 
encompasses MCP750 only.

The MCP750 single-board computer is based on the PowerPC MPC750 (Arthur)
microprocessors.  The series part numbers are of the form:

    MCP750-nnnn

    where
        nnnn = ECC DRAM size (DRAM contained on RAM300 module)
            1222 =  16MB
            1232 =  32MB
            1242 =  64MB
            1252 = 128MB
            1262 = 256MB

The MCP750 transition module designation is TMCP700-001.  The transition
module contains industry standard connector access to the IEEE 1284
parallel port, a single mouse/keyboard connector, two RJ45 connectors
providing access to the asynchronous serial ports configured as EIA DTE,
and two HD-26 connectors providing access to the serial ports.  These
serial ports, labeled as Serial 3 and Serial 4 on the face plate of the
TMCP700, are individually EIA-232, EIA530, V.35, or X.21 DCE or DTE
requiring the installation of Motorola's Serial Interface Modules (SIMs).
For more information refer to the Motorola manual 
\f2"TMCP 700 Transition Module Installation and Use"\f1.


The BAT registers are not supported in the current cache management strategy;
therefore, they can best be used for non-cacheable, data-only address regions.

.SS "Boot ROMS"
The MCP750 boards have two sets of flash EEPROM (FLASH).  One set of two AMD
Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's s
PPC1-Bug.  The other set of E28f400 FLASH is soldered in.  The VxWorks boot
kernel resides in the soldered FLASH.  See \f2Hardware Details: ROM
Considerations\f1 for information about loading and writing the boot kernel
image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
MCP750
.sp .5
Jumper	Function	Description
_
J6	ROM controller	T{
Install the jumper across pins 2 and 3 to select the socketed FLASH.
Install the jumper across pins 1 and 2 to select the soldered FLASH
(factory configuration).
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MCP750 are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Processors	T{
MPC750; 66MHz bus clock
T}
L2 Cache	T{
1MB in-line cache, write-through only.
T}
FLASH	T{
4MB or 8MB soldered (64-bit wide) on RAM300 mezzanine, 1MB socketed 
(16-bit wide).  Soldered used for VxWorks boot image.
T}
DRAM	T{
16, 32, 64, 128, 256MB, two-way interleaved; auto-sized or fixed
T}
NVRAM	T{
8KB (MK48T59/559)
8KB
T}
Peripherals	T{
serial ports COM1 and COM2;
two sync/async serial ports;
AUI or 10baseT/100baseTX Ethernet interface;
PS/2 floppy disk port;
Primary ATA/EIDE port and Compact Flash;
Secondary ATA/EIDE Port;
USB ports 1 and 2
T}
ISA Interface	T{
full 64KB memory and I/O space
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
Miscellaneous	T{
RESET switch
T}
.TE

.SS "PCI Autoconfiguration"

The board support package for the MCP750 handles automatic
detection and configuration of compact PCI devices.  In
particular, it performs the following:

.IP "1)"
Probes the host PCI bridge for all devices on the host
PCI bus (bus zero).  Note that among the devices on bus
zero might be PCI-PCI bridges.  These bridges are probed
as well and recursive probing occurs until all devices
and bridges are found. 

.IP "2)"
Memory is assigned to each device and sub-bridge found.
For devices, each Base Address Register (BAR) is queried.
Memory or I/O space (or both) is allocated for each BAR
which has been implemented.

.IP "3)"
Complete initialization of the devices is performed,
including cache Line size, command register, latency timer,
interrupt line and base address registers (0 through 5).
PCI-PCI bridges are initialized with the correct primary
bus, secondary bus and subordinate bus designation.  In
short, the entire bridge/device "tree" rooted at the host
pci bridge is completely configured and ready for driver
access.

.SS "PCI Autoconfiguration Roll Call"
A new feature to the PCI autoconfiguration is "roll call".  If you
expect to find a certain number of specific devices identified by
device/vendor ID during PCI autoconfiguration you can enter the
information into a roll call list.  For example assume that you
know that the autoconfiguration process should find 4 different
devices with device/vendor ID of 0x00461011 (this would be the
Dec2155x device).  You want PCI autoconfiguration to "wait" until
it finds at least this many but you don't want it to wait more
than 20 seconds.  If 20 seconds have elapsed and 4 different
Dec2155x chips have not appeared in the bus enumeration process,
you would like the PCI autoconfiguration process to proceed
anyway.

You would construct the "roll call" list in "config.h" as shown
below:

#define ROLL_CALL_MAX_DURATION 20  

#define PCI_ROLL_CALL_LIST_ENTRIES \
{ 4, 0x00461011 },


The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20
seconds should elapse before proceeding on with the
autoconfiguration, even though less than 4 Dec2155x devices have
been found.

You can see the entry { 4, 0x00461011 } which says that you expect
to find at least 4 devices whose device/vendor ID is 0x00461011.
Note that "mcpx750.h" contains defines for some device/vendor IDs,
such a define could be used here instead of a hard-coded
device/vendor ID.

Also note that this list can be extended so more than one device/
vendor ID is identified with possibly a different count.

If the list is empty (except for the termination entry) then there
is no roll call waiting performed, regardless of the setting of
ROLL_CALL_MAX_DURATION.

The roll call feature can be useful for devices which are slow to
appear on the cPCI bus.  For example, MCPN750 CPU boards (which
contain the Dec2155x nontransparent PCI bridge) will not be
visible to an MCP750 master which is enumerating the bus until the
MCPN750 clears the "primary access lock-out" bit in the Dec2155x chip
control 0 register.  If the MCP750's bus enumeration occurs
before the MCPN750 software unlocks the Dec2155x, then the MCP750
will not know the MCPN750 is present and will not configure it.
The roll call feature allows for bus enumeration polling until the
specified devices actually appear.  Note that roll call may not
always be required for the example just presented.  Some system
configurations and timings may work without using the roll call
feature.  

.SS "Shared Memory Support"

The MCP750 and MPCN750 supports shared memory backplane communication.
The Wind River documentation provides a great deal of information
regarding shared memory concepts.  The section below provides tutorial
style information regarding the setup of a shared memory system
involving the MCP750 and MCPN750.

Setting up a working shared memory system involves proper setting of
certain "config.h" parameters and proper setting of boot parameters
via the "c" command from the boot prompt.  There are three components
involved in shared memory communication which must be configured
properly to create a working system:

.IP "Anchor:"
This is an area of memory which must be accessible to all nodes
participating in shared memory backplane communication.  The anchor
points to the actual shared memory buffer pool which must be located
in the same memory space as the anchor itself.  The associated
"config.h" parameter is SM_ANCHOR_ADRS.  In certain configurations,
nonzero nodes will "poll" for the location of the anchor.  "config.h"
defines which comes into play for polling are SM_OFF_BOARD and
SYS_SM_SYSTEM_MEM_POLL.

.IP "Master node:"
This node is always designated as node zero.  It is the node which
sets up the anchor and shared memory pool.  Once the anchor and shared
memory pool is set up, the master node acts as a peer with the other
nodes.  The node number (0 in this case) is one of the boot parameters
which can be set up with the "c" command from the bootline prompt.

.IP "Sequential addressing:"
This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is
used when sequential IP addresses are assigned to the participating
nodes.  Node zero is assigned the lowest IP address, followed by nodes
1, 2 etc. which are assigned the subsequent and sequential IP addresses.
The advantage of sequential addressing is that fewer boot parameters
must be specified to configure the system.
.LP

The following restrictions apply to shared memory configurations.

.IP "1)"
Node zero must not boot over the shared memory interface.  Only
nonzero nodes are allowed to boot over the shared memory "sm"
interface.

.IP "2)"
The location of the anchor must be statically determinable by the
master node (node 0).  That is, the location of the anchor must
either be a build-time static parameter or it must be able to
be communicated to the master node via the "sm=xxxxxxxx" boot
configuration parameter.  The nonzero nodes need not know the
location of the anchor at build or boot time but can be configured
to poll for the anchor dynamically.
.LP

Note:  Another piece of shared memory terminology is "host node".
The "host node" is the node which configures the compact PCI bus
during startup initialization.  In a system consisting of an MCP750
and one or more MCPN750s, the "host node" is the MCP750.  Don't confuse
"host node" with "master node".  "Master node" is simply a synonym for