mcpx750.h

WINDRIVER MCP750 BSP

#   define DEC2155X_PRI_INT_TO_CPCI_INTA 0x00
#   define DEC2155X_PRI_INT_TO_CPCI_INTB 0x01
#   define DEC2155X_PRI_INT_TO_CPCI_INTC 0x02
#   define DEC2155X_PRI_INT_TO_CPCI_INTD 0x03

#   define DEC2155X_HW_INT_ROUTING_ADRS (ISA_MSTR_IO_LOCAL + 0x832)
#   define DEC2155X_CPCI_HW_INT_ROUTING_VAL DEC2155X_PRI_INT_TO_CPCI_INTA

#   define DEC2155X_CHP_CTRL0_VAL 0x0000
#   define DEC2155X_CHP_CTRL1_VAL 0x0000

#   define DEC2155X_PRI_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
			       DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
			       DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
			       DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
			       DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
			       DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
			       DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)

#   define DEC2155X_SEC_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
			       DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
			       DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
			       DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
			       DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
			       DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
			       DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)

#endif /* INCLUDE_DEC2155X */

/* Interrupt bases  */

#define ISA_INTERRUPT_BASE	0x00
#define EXT_INTERRUPT_BASE	0x10
#define TIMER_INTERRUPT_BASE	0x20
#define IPI_INTERRUPT_BASE	0x24
#define ERR_INTERRUPT_BASE	0x28
#define ESCC_INTERRUPT_BASE	0x00

#define DEC2155X_INTERRUPT_BASE 0x60

/* interrupt Level definitions */

/* ISA interrupt defines (NOTE: these are int. NUMBERS, not levels) */

#ifdef CONFIG1_ISA_INT_TYPE  /* Config1 ISA int levels (e.g. MCP750 ) */

    /* programmable timer interrupt level */

#   define PIT_INT_LVL			( 0x00 + ISA_INTERRUPT_BASE )

    /* com port 2 interrupt level */

#   define COM2_INT_LVL 		( 0x03 + ISA_INTERRUPT_BASE )

    /* com port 1 interrupt level */

#   define COM1_INT_LVL 		( 0x04 + ISA_INTERRUPT_BASE )

    /* floppy interrupt level */

#   define FD_INT_LVL			( 0x06 + ISA_INTERRUPT_BASE )

    /* parallel port interrupt level (not supported ) */

#   define PP_INT_LVL			( 0x07 + ISA_INTERRUPT_BASE )

    /* z8536 timer interrupt level (shared with z85230) */

#   define Z8536_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )

    /* z85230 ESCC interrupt level (shared with z8536) */

#   define Z85230_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )

    /* Universal Serial Bus interrupt level (not supported) */

#   define USB_INT_LVL			( 0x0b + ISA_INTERRUPT_BASE )

    /* mouse interrupt ( currently not supported ) */

#   define MOUSE_INT_LVL		( 0x0c + ISA_INTERRUPT_BASE )

#endif /* Config1 ISA int levels (e.g. MCP750 ) */


#ifdef CONFIG2_ISA_INT_TYPE  /* Config2 ISA int levels (e.g. MCPN750 ) */

    /* programable timer interrupt level */

#   define PIT_INT_LVL			( 0x00 + ISA_INTERRUPT_BASE )

    /* COM2 and COM4 UART interrupt level */

#   define COM2_INT_LVL 		( 0x03 + ISA_INTERRUPT_BASE )
#   define COM4_INT_LVL 		( 0x03 + ISA_INTERRUPT_BASE )

    /* COM1 and COM3 UART interrupt level */

#   define COM1_INT_LVL 		( 0x04 + ISA_INTERRUPT_BASE )
#   define COM3_INT_LVL 		( 0x04 + ISA_INTERRUPT_BASE )

    /* Abort button interrupt level (not supported) */

#   define ABORT_INT_LVL		( 0x08 + ISA_INTERRUPT_BASE )

    /* Universal Serial Bus interrupt level (not supported) */

#   define USB_INT_LVL			( 0x0b + ISA_INTERRUPT_BASE )

#endif /* Config2 ISA int levels (e.g. MCPN750 ) */

#   ifdef	INCLUDE_ATA

    /* IDE controller interrupt level */

#	define	IDE_CNTRLR0_INT_LVL	( 0x0e + ISA_INTERRUPT_BASE )
#	define	IDE_CNTRLR1_INT_LVL	( 0x0f + ISA_INTERRUPT_BASE )
#   endif	/* INCLUDE_ATA */

/* ISA interrupt base */

#define INT_VEC_IRQ0		0x00	/* vector for IRQ0 */

/* ISA interrupt vectors */

#ifdef CONFIG1_ISA_INT_TYPE  /* Config1 ISA int vectors (e.g. MCP750 ) */

#   define PIT_INT_VEC		( INT_VEC_IRQ0 + PIT_INT_LVL )
#   define COM2_INT_VEC 	( INT_VEC_IRQ0 + COM2_INT_LVL )
#   define COM1_INT_VEC 	( INT_VEC_IRQ0 + COM1_INT_LVL )
#   define FD_INT_VEC		( INT_VEC_IRQ0 + FD_INT_LVL )
#   define PP_INT_VEC		( INT_VEC_IRQ0 + PP_INT_LVL )
#   define Z8536_INT_VEC	( INT_VEC_IRQ0 + Z8536_INT_LVL )
#   define Z85230_INT_VEC	( INT_VEC_IRQ0 + Z85230_INT_LVL )
#   define USB_INT_VEC		( INT_VEC_IRQ0 + USB_INT_LVL )
#   define MOUSE_INT_VEC	( INT_VEC_IRQ0 + MOUSE_INT_LVL )
#   ifdef	INCLUDE_ATA
#	define IDE_CNTRLR0_INT_VEC	( INT_VEC_IRQ0 + IDE_CNTRLR0_INT_LVL )
#	define IDE_CNTRLR1_INT_VEC	( INT_VEC_IRQ0 + IDE_CNTRLR1_INT_LVL )
#   endif	/* INCLUDE_ATA */

#endif /* Config1 ISA int vectors (e.g. MCP750 ) */

#ifdef CONFIG2_ISA_INT_TYPE  /* Config2 ISA int vectors (e.g. MCPN750 ) */

#   define PIT_INT_VEC		( INT_VEC_IRQ0 + PIT_INT_LVL )
#   define COM2_INT_VEC 	( INT_VEC_IRQ0 + COM2_INT_LVL )
#   define COM4_INT_VEC 	( INT_VEC_IRQ0 + COM4_INT_LVL )
#   define COM1_INT_VEC 	( INT_VEC_IRQ0 + COM1_INT_LVL )
#   define COM3_INT_VEC 	( INT_VEC_IRQ0 + COM3_INT_LVL )
#   define ABORT_INT_VEC	( INT_VEC_IRQ0 + ABORT_INC_LVL )
#   define USB_INT_VEC		( INT_VEC_IRQ0 + USB_INT_LVL )
#   ifdef	INCLUDE_ATA
#	define IDE_CNTRLR0_INV_VEC	( INT_VEC_IRQ0 + IDE_CNTRLR0_INT_LVL )
#	define IDE_CNTRLR1_INT_VEC	( INT_VEC_IRQ0 + IDE_CNTRLR1_INT_LVL )
#   endif	/* INCLUDE_ATA */

#endif /* Config2 ISA int vectors */

/* Timer interrupt vectors */

#define TIMER0_INT_VEC		( INT_VEC_IRQ0 + TIMER0_INT_LVL )

/* MPIC interrupt levels */

#ifdef CONFIG1_MPIC_INT_TYPE  /* Config1 MPIC int levels (e.g. MCP750 ) */

    /* PIB (8259) interrupt connection level */

#   define PIB_INT_LVL		( 0x00 + EXT_INTERRUPT_BASE )

    /* Falcon-ECC error interrupt level */

#   define ECC_INT_LVL		( 0x01 + EXT_INTERRUPT_BASE )

    /* ethernet interrupt level */

#   define LN_INT_LVL		( 0x02 + EXT_INTERRUPT_BASE )

    /* PCI Mezzanine Card interrupt level */

#   define PMC_INT_LVL		( 0x03 + EXT_INTERRUPT_BASE )

    /* Watchdog Timer Level 1 interrupt level */

#   define WDT1_INT_LVL 	( 0x04 + EXT_INTERRUPT_BASE )

    /* CompactPCI PRST# signal level */

#   define CPCI_PRST_		( 0x05 + EXT_INTERRUPT_BASE )

    /* CompactPCI FAL# level */

#   define CPCI_FAL_		( 0x06 + EXT_INTERRUPT_BASE )

    /* CompactPCI DEG# level */

#   define CPCI_DEG_		( 0x07 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTA# level */

#   define CPCIA_INT_LVL	( 0x08 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTB# level */

#   define CPCIB_INT_LVL	( 0x09 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTC# level */

#   define CPCIC_INT_LVL	( 0x0a + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTD# level */

#   define CPCID_INT_LVL	( 0x0b + EXT_INTERRUPT_BASE )

#   define MAX_MPIC_INT_LVL	(EXT_INTERRUPT_BASE + 0xb)

#endif /* Config1 MPIC int levels (e.g. MCP750 ) */

#ifdef CONFIG2_MPIC_INT_TYPE  /* Config2 MPIC int levels (e.g. MCPN750 ) */

    /* PIB (8259) interrupt connection */

#   define PIB_INT_LVL		( 0x00 + EXT_INTERRUPT_BASE )

    /* Falcon-ECC error interrupt */

#   define ECC_INT_LVL		( 0x01 + EXT_INTERRUPT_BASE )

    /* ethernet interrupt level */

#   define LN_INT_LVL		( 0x02 + EXT_INTERRUPT_BASE )

    /* Watchdog Timer Level 1 interrupt level */

#   define WDTL1_INT_LVL	( 0x03 + EXT_INTERRUPT_BASE )

    /* 21554 Secondary PCI Bus interrupt level */

#   define PCI2_INT_LVL 	( 0x04 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTA# */

#   define CPCIA_INT_LVL	( 0x05 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTB# */

#   define CPCIB_INT_LVL	( 0x06 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTC# */

#   define CPCIC_INT_LVL	( 0x07 + EXT_INTERRUPT_BASE )

    /* CompactPCI Bus INTD# */

#   define CPCID_INT_LVL	( 0x08 + EXT_INTERRUPT_BASE )

    /* PMC1 INTA#, PMC2 INTB# */

#   define PMC1A_INT_LVL	( 0x09 + EXT_INTERRUPT_BASE )
#   define PMC2B_INT_LVL	( 0x09 + EXT_INTERRUPT_BASE )

    /* PMC1 INTB#, PMC2 INTC# */

#   define PMC1B_INT_LVL	( 0x0a + EXT_INTERRUPT_BASE )
#   define PMC2C_INT_LVL	( 0x0a + EXT_INTERRUPT_BASE )

    /* PMC1 INTC#, PMC2 INTD# */

#   define PMC1C_INT_LVL	( 0x0b + EXT_INTERRUPT_BASE )
#   define PMC2D_INT_LVL	( 0x0b + EXT_INTERRUPT_BASE )

    /* PMC1 INTD#, PMC2 INTA# */

#   define PMC1D_INT_LVL	( 0x0c + EXT_INTERRUPT_BASE )
#   define PMC2A_INT_LVL	( 0x0c + EXT_INTERRUPT_BASE )

#   define MAX_MPIC_INT_LVL	(EXT_INTERRUPT_BASE + 0xc)

#endif /* Config2 MPIC int levels (e.g. MCPN750 ) */

/* Timer Interrupt (IPI0) */

#define TIMER0_INT_LVL		  	( 0x00 + TIMER_INTERRUPT_BASE )

#define DEC2155X_DOORBELL0_INT_LVL	( 0x00 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL1_INT_LVL	( 0x01 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL2_INT_LVL	( 0x02 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL3_INT_LVL	( 0x03 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL4_INT_LVL	( 0x04 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL5_INT_LVL	( 0x05 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL6_INT_LVL	( 0x06 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL7_INT_LVL	( 0x07 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL8_INT_LVL	( 0x08 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL9_INT_LVL	( 0x09 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL10_INT_LVL 	( 0x0a + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL11_INT_LVL 	( 0x0b + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL12_INT_LVL 	( 0x0c + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL13_INT_LVL 	( 0x0d + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL14_INT_LVL 	( 0x0e + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL15_INT_LVL 	( 0x0f + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PWR_MGMT_INT_LVL	( 0x10 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_I2O_INT_LVL		( 0x11 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PG_CRSSNG_INT_LVL	( 0x12 + DEC2155X_INTERRUPT_BASE )

/* MPIC interrupt vectors */

#ifdef CONFIG1_MPIC_INT_TYPE  /* Config1 MPIC int vectors (e.g. MCP750 ) */

#   define PIB_INT_VEC			( INT_VEC_IRQ0 + PIB_INT_LVL )
#   define ECC_INT_VEC			( INT_VEC_IRQ0 + ECC_INT_LVL )
#   define LN_INT_VEC			( INT_VEC_IRQ0 + LN_INT_LVL )
#   define PMC_INT_VEC			( INT_VEC_IRQ0 + PMC_INT_LVL )
#   define WDT1_INT_VEC 		( INT_VEC_IRQ0 + WDT1_INT_LVL )
#   define CPCI_PRST_VEC		( INT_VEC_IRQ0 + CPCI_PRST_LVL )
#   define CPCI_FAL_VEC 		( INT_VEC_IRQ0 + CPCI_FAL_LVL )
#   define CPCI_DEG_VEC 		( INT_VEC_IRQ0 + CPCI_DEG_LVL )
#   define CPCIA_INT_VEC		( INT_VEC_IRQ0 + CPCIA_INT_LVL )
#   define CPCIB_INT_VEC		( INT_VEC_IRQ0 + CPCIB_INT_LVL )
#   define CPCIC_INT_VEC		( INT_VEC_IRQ0 + CPCIC_INT_LVL )
#   define CPCID_INT_VEC		( INT_VEC_IRQ0 + CPCID_INT_LVL )

#endif /* Config1 MPIC int vectors (e.g. MCP750 ) */

#ifdef CONFIG2_MPIC_INT_TYPE  /* Config2 MPIC int vectors (e.g. MCPN750 ) */

#   define PIB_INT_VEC			( INT_VEC_IRQ0 + PIB_INT_LVL )
#   define ECC_INT_VEC			( INT_VEC_IRQ0 + ECC_INT_LVL )
#   define LN_INT_VEC			( INT_VEC_IRQ0 + LN_INT_LVL )
#   define WDT1_INT_VEC 		( INT_VEC_IRQ0 + WDT1_INT_LVL )
#   define PCI2_INT_VEC 		( INT_VEC_IRQ0 + PCI2_INT_LVL )
#   define CPCIA_INT_VEC		( INT_VEC_IRQ0 + CPCIA_INT_LVL )
#   define CPCIB_INT_VEC		( INT_VEC_IRQ0 + CPCIB_INT_LVL )
#   define CPCIC_INT_VEC		( INT_VEC_IRQ0 + CPCIC_INT_LVL )
#   define CPCID_INT_VEC		( INT_VEC_IRQ0 + CPCID_INT_LVL )
#   define PMC1A_INT_VEC		( INT_VEC_IRQ0 + PMC1A_INT_LVL )
#   define PMC2B_INT_VEC		( INT_VEC_IRQ0 + PMC2B_INT_LVL )
#   define PMC1B_INT_VEC		( INT_VEC_IRQ0 + PMC1B_INT_LVL )
#   define PMC2C_INT_VEC		( INT_VEC_IRQ0 + PMC2C_INT_LVL )
#   define PMC1C_INT_VEC		( INT_VEC_IRQ0 + PMC1C_INT_LVL )
#   define PMC2D_INT_VEC		( INT_VEC_IRQ0 + PMC2D_INT_LVL )
#   define PMC1C_INT_VEC		( INT_VEC_IRQ0 + PMC1C_INT_LVL )
#   define PMC2A_INT_VEC		( INT_VEC_IRQ0 + PMC2A_INT_LVL )
#endif /* Config2 MPIC int vectors (e.g. MCPN750 ) */

#define DEC2155X_DOORBELL0_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL0_INT_LVL)
#define DEC2155X_DOORBELL1_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL1_INT_LVL)
#define DEC2155X_DOORBELL2_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL2_INT_LVL)
#define DEC2155X_DOORBELL3_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL3_INT_LVL)
#define DEC2155X_DOORBELL4_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL4_INT_LVL)
#define DEC2155X_DOORBELL5_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL5_INT_LVL)
#define DEC2155X_DOORBELL6_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL6_INT_LVL)
#define DEC2155X_DOORBELL7_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL7_INT_LVL)
#define DEC2155X_DOORBELL8_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL8_INT_LVL)
#define DEC2155X_DOORBELL9_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL9_INT_LVL)
#define DEC2155X_DOORBELL10_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL10_INT_LVL)
#define DEC2155X_DOORBELL11_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL11_INT_LVL)
#define DEC2155X_DOORBELL12_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL12_INT_LVL)
#define DEC2155X_DOORBELL13_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL13_INT_LVL)
#define DEC2155X_DOORBELL14_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL14_INT_LVL)
#define DEC2155X_DOORBELL15_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL15_INT_LVL)
#define DEC2155X_PWR_MGMT_INT_VEC   (INT_VEC_IRQ0 + DEC2155X_PWR_MGMT_INT_LVL)
#define DEC2155X_I2O_INT_VEC        (INT_VEC_IRQ0 + DEC2155X_I2O_INT_LVL)
#define DEC2155X_PG_CRSSNG_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_PG_CRSSNG_INT_LVL)

/*
 * Address range definitions for PCI bus.
 *
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCI_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_HI_ADRS))

#define SYS_REG_SIOP_HW_REGS	{0,0,0,0,0,1,0,0,0,0,0}

#ifdef SYS_SM_ANCHOR_POLL_LIST
#   ifndef _ASMLANGUAGE
        /*
         * Shared memory anchor polling list
         */

        typedef struct _SYS_SM_ANCHOR_POLLING_LIST
            {
            UINT devVend;
            UINT subIdVend;
            } SYS_SM_ANCHOR_POLLING_LIST;
#   endif
#endif

#ifndef _ASMLANGUAGE
    /*
     * Shared memory device list
     */

    typedef struct _SYS_SM_DEV_LIST
        {
        UINT devVend;
        UINT subIdVend;
        } SYS_SM_DEV_LIST;
#endif

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
				     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )

#ifdef __cplusplus
}
#endif

#endif /* __INCmcpx750h */