mcpx750.h

WINDRIVER MCP750 BSP

#   define SYS_REG_BLRR_RSV1	0x80	/* Reserved */
#   define SYS_REG_BLRR_SWSRST	0x40	/* Software Soft Reset */
#   define SYS_REG_BLRR_SWHRST	0x20	/* Software Hard Reset, port 92 */
#   define SYS_REG_BLRR_CMDRST	0x10	/* Compact PCI command reset */
#   define SYS_REG_BLRR_CPCIRST 0x08	/* Compact PCI hard reset (RST#) */
#   define SYS_REG_BLRR_WDT2	0x04	/* Watchdog Timer Level 2 Reset */
#   define SYS_REG_BLRR_FBTN	0x02	/* Front Panel Button Reset */
#   define SYS_REG_BLRR_PWRON	0x01	/* Power-On Reset */
#endif

/* cPCI Geographic Address Register */

#ifdef CONFIG2_SYS_REG_CPGAR
#   define SYS_REG_CPGAR	((char *)(ISA_MSTR_IO_LOCAL + 0x0830))
#   define SYS_REG_GPGAR_MSK	0x1f
#endif

#ifdef CONFIG2_SYS_REG_PINTA
#   define SYS_REG_PINTA	((char *)(ISA_MSTR_IO_LOCAL + 0x0832))
#   define SYS_REG_PINTA_MSK	0x00000003
#   define SYS_REG_GPGAR_INTA	0x0	/* INTA# routine */
#   define SYS_REG_GPGAR_INTB	0x1	/* INTB# routine */
#   define SYS_REG_GPGAR_INTC	0x2	/* INTC# routine */
#   define SYS_REG_GPGAR_INTD	0x3	/* INTD# routine */
#endif

#ifdef CONFIG2_SYS_REG_ABRTBTN
#   define SYS_REG_ABRTBTN	((char *)(ISA_MSTR_IO_LOCAL + 0x0845))
#   define SYS_REG_ABRTBTN_MSK		0x80
#   define SYS_REG_ABRTBTN_DOWN 	0x00
#   define SYS_REG_ABRTBTN_UP		0x00
#endif

#ifdef CONFIG2_SYS_REG_BRDFAIL_LED
#   define SYS_REG_BRDFAIL_LED	((char *)(ISA_MSTR_IO_LOCAL + 0x0846))
#   define SYS_REG_BRDFAIL_LED_ON	0x40
#endif


/* Assembly define for L2 cache */

#define SYS_REG_SXCCR_A 	(FALCON_BASE_ADRS + 0x8000)

/* defines for L2 cache routines */

#define SYS_REG_SXCCR		((unsigned char *)(FALCON_BASE_ADRS + 0x8000))

#define L2_DISABLE		0x80
#define L2_RESET		0x40
#define L2_ENABLE		0x80
#define L2_FLUSH		0x10
#define L2_END_FLUSH		0x10
#define L2_FLUSH_LOOP		4100

/* z8536 I/O port bit mapping */

#ifdef CONFIG1_SYS_REG_BRDFAIL_LED
#   define	z8536_PORTA_BRDFAIL	0x40
#endif

#ifdef CONFIG1_PLANAR_ISA
#   define	z8536_PORTB_FUSE	0x40
#   define	z8536_PORTB_ABORT	0x80
#endif

/*
 * Raven Extensions to Standard PCI Header
 *
 * Type declarations for the PCI Header and the macros in regards to the
 * PCI BUS.  These definitions have been made with respect to PCI LOCAL
 * BUS SPECIFICATION REVISION 2.1.  Every device on the PCI BUS has to
 * support 256 bytes of configuration space of which the first 64 bytes
 * are a predefined header portion defined by the PCI commitee.  Bytes
 * 64 to 255 are dedicated to the device specific registers.
 *
 * Note: the PCI bus is inherently little endian.
 */

#define PCI_CFG_RAVEN_PSADD0	0x80
#define PCI_CFG_RAVEN_PSATT0	0x84
#define PCI_CFG_RAVEN_PSOFF0	0x86
#define PCI_CFG_RAVEN_PSADD1	0x88
#define PCI_CFG_RAVEN_PSATT1	0x8c
#define PCI_CFG_RAVEN_PSOFF1	0x8e
#define PCI_CFG_RAVEN_PSADD2	0x90
#define PCI_CFG_RAVEN_PSATT2	0x94
#define PCI_CFG_RAVEN_PSOFF2	0x96
#define PCI_CFG_RAVEN_PSADD3	0x98
#define PCI_CFG_RAVEN_PSATT3	0x9c
#define PCI_CFG_RAVEN_PSOFF3	0x9e

/* Raven MPC registers */

#define RAVEN_MPC_VENID 	0x00
#define RAVEN_MPC_DEVID 	0x02
#define RAVEN_MPC_REVID 	0x05
#define RAVEN_MPC_GCSR		0x08
#define RAVEN_MPC_FEAT		0x0a
#define RAVEN_MPC_MARB		0x0e
#define RAVEN_MPC_PADJ		0x13
#define RAVEN_MPC_MEREN 	0x22
#define RAVEN_MPC_MERST 	0x27
#define RAVEN_MPC_MERAD 	0x28
#define RAVEN_MPC_MERAT 	0x2e
#define RAVEN_MPC_PIACK 	0x30
#define RAVEN_MPC_MSADD0	0x40
#define RAVEN_MPC_MSOFF0	0x44
#define RAVEN_MPC_MSATT0	0x47
#define RAVEN_MPC_MSADD1	0x48
#define RAVEN_MPC_MSOFF1	0x4c
#define RAVEN_MPC_MSATT1	0x4f
#define RAVEN_MPC_MSADD2	0x50
#define RAVEN_MPC_MSOFF2	0x54
#define RAVEN_MPC_MSATT2	0x57
#define RAVEN_MPC_MSADD3	0x58
#define RAVEN_MPC_MSOFF3	0x5c
#define RAVEN_MPC_MSATT3	0x5f
#define RAVEN_MPC_WDT1CNTL	0x60
#define RAVEN_MPC_WDT2CNTL	0x68
#define RAVEN_MPC_GPREG0_U	0x70
#define RAVEN_MPC_GPREG0_L	0x74
#define RAVEN_MPC_GPREG1_U	0x78
#define RAVEN_MPC_GPREG1_L	0x7c

/*
 * Raven register bit masks
 *
 * Bits marked with 'C' indicate conditions which can be cleared by
 * writing a 1 to the bits.
 */

/* Raven MPC Error Enable (MEREN) register bit masks */

#define RAVEN_MPC_MEREN_RTAI	0x0001	/* PCI mstr Recvd Target Abort Int */
#define RAVEN_MPC_MEREN_SMAI	0x0002	/* PCI mstr Signld Target Abort Int */
#define RAVEN_MPC_MEREN_SERRI	0x0004	/* PCI System Error Int */
#define RAVEN_MPC_MEREN_PERRI	0x0008	/* PCI Parity Error Int */
#define RAVEN_MPC_MEREN_MDPEI	0x0010	/* MPC Data Parity Error Int */
#define RAVEN_MPC_MEREN_MATOI	0x0020	/* MPC Address Bus Time-out Int */
#define RAVEN_MPC_MEREN_RTAM	0x0100	/* RTAI machine check enable */
#define RAVEN_MPC_MEREN_SMAM	0x0200	/* SMAI machine check enable */
#define RAVEN_MPC_MEREN_SERRM	0x0400	/* SERRI machine check enable */
#define RAVEN_MPC_MEREN_PERRM	0x0800	/* PERRI machine check enable */
#define RAVEN_MPC_MEREN_MDPEM	0x1000	/* MDPEI machine check enable */
#define RAVEN_MPC_MEREN_MATOM	0x2000	/* MATOI machine check enable */
#define RAVEN_MPC_MEREN_DFLT	0x4000	/* Default MPC Master ID select */
#define RAVEN_MPC_MEREN_VALID	0x7F3F	/* Mask for valid MEREN bits */

/* Raven MPC Error Status (MERST) register bit masks */

#define RAVEN_MPC_MERST_RTA	0x01	/* C PCI mstr Recvd Target Abort */
#define RAVEN_MPC_MERST_SMA	0x02	/* C PCI mstr Signld Target Abort */
#define RAVEN_MPC_MERST_SERR	0x04	/* C PCI System Error */
#define RAVEN_MPC_MERST_PERR	0x08	/* C PCI Parity Error */
#define RAVEN_MPC_MERST_MDPE	0x10	/* C MPC Data Bus Parity Error */
#define RAVEN_MPC_MERST_MATO	0x20	/* C MPC Address Bus Time-out */
#define RAVEN_MPC_MERST_OVF	0x80	/* C Error Status Overflow */
#define RAVEN_MPC_MERST_VALID	0xBF	/*   Mask for valid MERST bits */
#define RAVEN_MPC_MERST_CLR	0xBF	/*   Clears all errors */

/* Raven PCI Configuration Status register bit masks */

#define RAVEN_PCI_CFG_STATUS_FAST    0x0010  /*   Fast back-to-back capable */
#define RAVEN_PCI_CFG_STATUS_DPAR    0x0100  /* C Data prity error detected */
#define RAVEN_PCI_CFG_STATUS_SELTIM0 0x0200  /*   Device select timing bit 0 */
#define RAVEN_PCI_CFG_STATUS_SELTIM1 0x0400  /*   Device select timing bit 1 */
#define RAVEN_PCI_CFG_STATUS_SIGTA   0x0800  /* C Signalled Target Abort */
#define RAVEN_PCI_CFG_STATUS_RCVTA   0x1000  /* C Received Target Abort */
#define RAVEN_PCI_CFG_STATUS_RCVMA   0x2000  /* C Received Master Abort */
#define RAVEN_PCI_CFG_STATUS_SIGSE   0x4000  /* C Signalled System Error */
#define RAVEN_PCI_CFG_STATUS_RCVPE   0x8000  /* C Detected Parity Error */
#define RAVEN_PCI_CFG_STATUS_VALID   0xFF10  /*   Valid status bits */
#define RAVEN_PCI_CFG_STATUS_CLR     0xF900  /*   Clears all conditions */

/*
 * Falcon Register Offsets
 */

#define FALCON_DPE_LOG_REG 0x68
#define FALCON_DPE_ENA_REG 0x6a

#define FALCON_DPELOG    (1 << 7) /* assuming byte-wide access */
#define FALCON_DPE_CKALL (1 << 1) /* assuming byte-wode access */
#define FALCON_DPE_ME    (1 << 0) /* assuming byte-wide access */

/*
 * VIA Extensions to Standard PCI Header
 *
 * Type declarations for the PCI Header and the macros in regards to the
 * PCI BUS.  These definitions have been made with respect to PCI LOCAL
 * BUS SPECIFICATION REVISION 2.1.  Every device on the PCI BUS has to
 * support 256 bytes of configuration space of which the first 64 bytes
 * are a predefined header portion defined by the PCI commitee.  Bytes
 * 64 to 255 are dedicated to the device specific registers.
 *
 * Note: the PCI bus is inherently little endian.
 */

#define PCI_CFG_VIA_ISA_BC	0x40
#define PCI_CFG_VIA_ISA_TM	0x41
#define PCI_CFG_VIA_ISA_CC	0x42
#define PCI_CFG_VIA_ROM_DC	0x43
#define PCI_CFG_VIA_KEYBD_CC	0x44
#define PCI_CFG_VIA_DMA_C	0x45
#define PCI_CFG_VIA_MC1 	0x46
#define PCI_CFG_VIA_MC2 	0x47
#define PCI_CFG_VIA_MC3 	0x48
#define PCI_CFG_VIA_IDE_IR	0x4a
#define PCI_CFG_VIA_MEM_AC1	0x4c
#define PCI_CFG_VIA_MEM_AC2	0x4d
#define PCI_CFG_VIA_MEM_AC3	0x4e
#define PCI_CFG_VIA_EGLV_SEL	0x54

/* VIA ISA Test Mode register bit masks */

#define VIA_PCI_CFG_ISA_TM_MSK	0xff		/* Register Mask */
#define VIA_PCI_CFG_ISA_TM_P92	0x20		/* Port 92 Enable */

/* VIA Miscellaneous Control 1 register bit masks */

#define VIA_PCI_CFG_MC1_MSK	0xff		/* Register Mask */
#define VIA_PCI_CFG_MC1_POST_M	0x01		/* Powt Memory Write Enable */

/* VIA Miscellaneous Control 2 register bit masks */

#define VIA_PCI_CFG_MC2_4D0_PORT 0x20		/* Enable 4d0/4d1 port */

/* VIA Miscellaneous Control 3 register bit masks */

#define VIA_PCI_CFG_MC3_MSK	0xff		/* Register Mask */
#define VIA_PCI_CFG_MC3_RTC_E	0x08		/* RTC Port 74/75 Enable */
#define VIA_PCI_CFG_MC3_512_M	0x01		/* 512K PCI Memory Decode */

/* VIA IDE Interrupt Routing register bit masks */

#define VIA_PCI_CFG_IDE_MSK	0xff		/* Register Mask */
#define VIA_PCI_CFG_IDE_SEC_15	0x04		/* IDE Second Channel IRQ15 */
#define VIA_PCI_CFG_IDE_PRI_14	0x00		/* IDE Primary Channel IRQ14 */

/* VIA ISA DMA/Master Memory Access Control 3 register bit masks */

#define VIA_PCI_CFG_MEM_AC3_MSK 0xff		/* Register Mask */
#define VIA_PCI_CFG_MEM_AC3_1M	0x0000		/* Top of Memory for ISA - 1M */
#define VIA_PCI_CFG_MEM_AC3_2M	0x1000		/* Top of Memory for ISA - 2M */
#define VIA_PCI_CFG_MEM_AC3_16M 0xf000		/* Top of Memory for ISA - 16M*/
#define VIA_PCI_CFG_MEM_0_7FFFF 0x0100		/* Forward 0 - 7FFFF to PCI */

/* VIA PCI-IRQ edge/level select bits (1 = edge, 0 = level) */

#define VIA_PCI_CFG_EGLV_LV 0x0f

/* VIA Legacy I/O Ports register bit masks */

#define VIA_ISA_PORT92_ADDRESS	(ISA_MSTR_IO_LOCAL + 0x92) /* Port 92 ADDRESS */
#define VIA_ISA_PORT92_RESET	0x01		/* Port 92 System Reset bit */

/*
 * PMC Span DEC21150 PCI-to-PCI Bridge device-specific registers
 *
 * These registers are in Configuration Space and are extensions to a
 * standard type 1 PCI header.
 */

#define PCI_CFG_DEC21150_CHIP_CTRL 0x40
#define PCI_CFG_DEC21150_DIAG_CTRL 0x41
#define PCI_CFG_DEC21150_ARB_CTRL  0x42
#define PCI_CFG_DEC21150_EVNT_DSBL 0x64
#define PCI_CFG_DEC21150_GPIO_DOUT 0x65
#define PCI_CFG_DEC21150_GPIO_CTRL 0x66
#define PCI_CFG_DEC21150_GPIO_DIN  0x67
#define PCI_CFG_DEC21150_SEC_CLK   0x68     /* secondary clock controll reg */
#define PCI_CFG_DEC21150_SERR_STAT 0x6A

/* programmable interrupt controller (PIC) */

#define PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* programmable interrupt timers */

#define PIT_BASE_ADR		SL82565_TMR1_CNT0	/* timeraddrs */
#define PIT_REG_ADDR_INTERVAL	1
#define PIT_CLOCK		1193180

/* serial ports (COM1 - COM4) */

#ifdef INCLUDE_I8250_SIO
#   define COM1_BASE_ADR		pc87303_COM1	/* serial port 1 */
#   define COM2_BASE_ADR		pc87303_COM2	/* serial port 2 */

#   ifdef CONFIG2_PLANAR_ISA
#	define COM3_BASE_ADR		pc87303_COM3	/* serial port 3 */
#	define COM4_BASE_ADR		pc87303_COM4	/* serial port 4 */
#   endif

#   define UART_REG_ADDR_INTERVAL	1	/* addr diff of adjacent regs */
#   ifdef CONFIG1_PLANAR_ISA
#	define N_UART_CHANNELS		2	/* No. serial I/O channels */
#   endif
#   ifdef CONFIG2_PLANAR_ISA
#	define N_UART_CHANNELS		4	/* No. serial I/O channels */
#   endif
#endif /* INCLUDE_I8250_SIO */

#ifdef INCLUDE_Z85230_SIO
#   define BAUD_CLK_FREQ	10000000	/* 10 MHz "P Clock" (fixed) */
#   define REG_8530_WRITE(reg,val) sysOutByte((UINT32)(reg), (UINT8)(val))
#   define REG_8530_READ(reg,pVal) *(UINT8 *)pVal = sysInByte((UINT32)reg)
#   define DATA_REG_8530_DIRECT
/* #	define Z8530_RESET_DELAY_COUNT 2000 */
#define Z8530_RESET_DELAY \
	{ \
	int i; \
	for (i = 0; i < Z8530_RESET_DELAY_COUNT; i++) \
		; /* do nothing */ \
	}
#endif /* INCLUDE_Z85230_SIO */

/* total number of serial ports */

#ifdef CONFIG1_PLANAR_ISA
#   if defined(INCLUDE_I8250_SIO) && defined(INCLUDE_Z85230_SIO)
#	define N_SIO_CHANNELS	4		/* No. serial I/O channels */
#   elif defined(INCLUDE_I8250_SIO)
#	define N_SIO_CHANNELS	2		/* No. serial I/O channels */
#   elif defined(INCLUDE_Z85230_SIO)
#	define N_SIO_CHANNELS	2		/* No. serial I/O channels */
#   endif
#endif

#ifdef CONFIG2_PLANAR_ISA
#   ifdef INCLUDE_I8250_SIO
#	define N_SIO_CHANNELS	4		/* No. serial I/O channels */
#   endif
#endif

#ifndef N_SIO_CHANNELS
#   define N_SIO_CHANNELS	0		/* No. serial I/O channels */
#endif

/* non-volatile (battery-backed) ram defines
 *
 * the top 16 bytes are used for the RTC registers
 */

#define BBRAM_ADRS		0		/* base address */
#define BBRAM_SIZE		0x1ff0		/* 8k NVRAM Total Size */

/* factory ethernet address */

#define BB_ENET 		((char *)(BBRAM_ADRS + 0x1f2c))

/* MK48TXX register settings */

/* flag register */

#define MK48T_FLAGS		((char *)(BBRAM_ADRS + 0x1ff0))

/* alarm clock registers, 4 1byte locations */

#define ALARM_CLOCK		((char *)(BBRAM_ADRS + 0x1ff2))

/* interrupt register */

#define MK48T_INTR		((char *)(BBRAM_ADRS + 0x1ff6))

/* watchdog timer register */

#define WD_TIMER		((char *)(BBRAM_ADRS + 0x1ff7))

/* MK48TXX bb time of day clk, 8 1byte locations */

#define TOD_CLOCK		((char *)(BBRAM_ADRS + 0x1ff8))

#define NV_RAM_IO_MAPPED	/* nvram is io mapped in ISA space */
#define NV_RAM_READ(x)		sysNvRead (x)
#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)
#define NV_RAM_LSB_REG		m48TXX_LSB_REG
#define NV_RAM_MSB_REG		m48TXX_MSB_REG
#define NV_RAM_DAT_REG		m48TXX_DAT_REG

/* ncr810/ncr825 delay loop count */

#define NCR810_DELAY_MULT	10

/* SUPER I/O defines */

#define SUPER_IO_BASE1		0x002e
#define SUPER_IO_BASE2		0x015c
#define SUPER_IO_KBC_BASE_ADR	0x60
#define SUPER_IO_KBC_CMND_ADR	0x64
#define SUPER_IO_FDC_BASEHI	0x03
#define SUPER_IO_FDC_BASELO	0xf0
#define SUPER_IO_COM1_BASEHI	0x03
#define SUPER_IO_COM1_BASELO	0xf8
#define SUPER_IO_COM2_BASEHI	0x02
#define SUPER_IO_COM2_BASELO	0xf8
#define SUPER_IO_PP_BASEHI	0x03
#define SUPER_IO_PP_BASELO	0xbc
#define SUPER_IO_FDC_PS2	0x40
#define SUPER_IO_PP_CFG 	0x12
#define SUPER_IO_ENBL_INTS	0x02

/* Dec 2155x defines */

#define DEC2155X_MAILBOX_INT_VEC (DEC2155X_DOORBELL0_INT_VEC + \
				     DEC2155X_SM_DOORBELL_BIT)
#ifdef INCLUDE_DEC2155X


#   define DEC2155X_BIST_VAL 0x00
#   define DEC2155X_PRI_PRG_IF_VAL 0x00
#   define DEC2155X_PRI_SUBCLASS_VAL 0x20
#   define DEC2155X_PRI_CLASS_VAL 0x0b
#   define DEC2155X_SEC_PRG_IF_VAL 0x00
#   define DEC2155X_SEC_SUBCLASS_VAL 0x80
#   define DEC2155X_SEC_CLASS_VAL 0x06
#   define DEC2155X_MAX_LAT_VAL 0x00
#   define DEC2155X_MIN_GNT_VAL 0xff