syscache.c

WINDRIVER MCP750 BSP

*
* sysL2CacheDisable - disable the L2 cache(s)
* 
* RETURNS: void
*
*/ 

void sysL2CacheDisable (void)
    {
    UINT cacheSize;

#if FALSE       /* lookasidecache not on MCP750 */
    if ((cacheSize = sysL2LookasideCacheSize()) != 0)
	{
	sysL2LookasideCacheDisable();
	}
#endif

    if ((cacheSize = sysL2InlineCacheSize()) != 0)
	{
	sysL2InlineCacheDisable();
	}
    }

/******************************************************************************
*
* sysL2LookasideCacheDisable - disable the L2 lookaside cache
*
* This routine disables the L2 lookaside cache if it was previously 
* initialized using sysL2CacheInit().  Calling this routine invalidates 
* the L2 tag bits.
*
* RETURNS: N/A
*
*/ 

LOCAL void sysL2LookasideCacheDisable (void)
    {
    unsigned char	regVal;
    int		  	temp;
    int			i;

    if (sysL2LookasideCacheSize() == 0)
	return;                          /* No cache to disable */

    /* Invalidate all L2 cache tags, clear the SXC_RST bit */

    regVal = *SYS_REG_SXCCR;
    regVal &= (~L2_RESET);
    *SYS_REG_SXCCR = regVal;

    for (i=0; i<=10; i++)
        temp = nop ( i );
 
    /* reset the SXC_RST bit in the cache control reg. */
    *SYS_REG_SXCCR |= L2_RESET;

    /* disable the L2 cache */
    regVal = *SYS_REG_SXCCR;
    regVal &= (~L2_DISABLE);
    *SYS_REG_SXCCR = regVal;
    }

/******************************************************************************
*
* sysL2InlineCacheDisable - disable the L2 in-line cache
*
* If the in-line cache is enabled, this routine disables it via the following
* steps:
*
* .IP "1."
* Flush by reading one word from each cache line within a cache
* enabled buffer.  Note that this buffer should be twice the size of
* the L2 cache to override the pseudo-LRU replacement algorithm.
* .IP "2."
* Turn of the cache enable bit in the L2CR.
*
* RETURNS: N/A
*
*/ 

LOCAL void sysL2InlineCacheDisable (void)
    {
    ULONG tmp;
    ULONG l2crVal;
    int i;

    if ((l2crVal = sysL2crGet()) & MPC750_L2CR_E)
	{
	if (vxHid0Get() & _PPC_HID0_DCE)
	    {
	    for (i = (2 * sysL2InlineCacheSize()); i >= 0; i -= 32 )
                    tmp = *((ULONG *)0 + i);
	    }
	sysL2crPut(l2crVal & ~MPC750_L2CR_E);
	}
    }

/******************************************************************************
*
* sysL2CacheFlush - flush the L2 cache(s)
*
* This routine flushes the L2 cache(s) if either or both were
* previously initialized using sysL2CacheInit().
*
* RETURNS: N/A
*
* SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()
*/
void sysL2CacheFlush (void)
    {
    UINT cacheSize;

    if ((cacheSize = sysL2InlineCacheSize()) != 0)
        sysL2InlineCacheFlush();
    }

/******************************************************************************
*
* sysL2InlineCacheFlush - flush the L2 cache(s)
*
* Flush by reading one word from each cache line within a cache
* enabled buffer.  Note that this buffer should be twice the size of
* the L2 cache to override the pseudo-LRU replacement algorithm.
*
* RETURNS: N/A
*
* SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()
*/
LOCAL void sysL2InlineCacheFlush (void)
    {
    int lockKey;
    register int i;
    register ULONG tmp;

    lockKey=intLock();
    if (CPU_TYPE == CPU_TYPE_750)
        {
        if (vxHid0Get() & _PPC_HID0_DCE)
            {
            /* flush the inline L2 cache */

            for (i = 2*sysL2InlineCacheSize() - 32; i >= 0; i -= 32 )
            tmp = *(ULONG *)(RAM_LOW_ADRS + i);
            }
        }
    else
        {
        sysMaxL2Flush();
        }
    intUnlock(lockKey);
    }

/******************************************************************************
*
* sysL2CacheInvFunc - Invalidate the L2 cache(s)
*
* This routine invalidates the L2 cache(s) if either or both were
* previously initialized using sysL2CacheInit().  Calling this
* routine invalidates the L2 tag bits.
*
* RETURNS: N/A
*
* SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()
*/

void sysL2CacheInvFunc (void)
    {
    UINT cacheSize;

    if ((cacheSize = sysL2InlineCacheSize()) != 0)
        sysL2InlineCacheInvFunc();
    }

/******************************************************************************
*
* sysL2InlineCacheInvFunc - Invalidate the L2 cache(s)
*
* Disables interrupts and calls the function to invalidate the L2 cache.
*
* RETURNS: N/A
*
* SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()
*/

LOCAL void sysL2InlineCacheInvFunc (void)
    {
    int lockKey;
    lockKey=intLock();
    sysMaxL2InvFunc();
    intUnlock(lockKey);
    }

/******************************************************************************
*
* sysL2LookasideCacheSize() - Determine size of the L2 lookaside cache.
*
* This function returns the size of the L2 lookaside cache.  If no L2
* lookaside cache is present, the size returned is zero so this function's
* return value can be used like a boolean to determine if the L2 lookaside
* cache is actually present.
*
* RETURNS: Size of L2 lookaside cache or zero if lookaside cache not present.
*
* NOTE: The L2 lookaside cache is sometimes referred to as the "glance" cache.
*/ 

LOCAL UINT sysL2LookasideCacheSize()
    {
    STATUS size;
    switch ( *SYS_REG_CCR & SYS_REG_CCR_SYSXC_MSK )
	{
        case SYS_REG_CCR_SYSXC_1024:
	    size = 0x100000;	    /* 1MB cache present */
	    break;
        case SYS_REG_CCR_SYSXC_512:     
	    size = 0x80000;         /* 512K cache present */
	    break;
        case SYS_REG_CCR_SYSXC_256:
	    size = 0x40000;         /* 256K cache present */
            break; 	           
        default:
            size = 0 ;              /* L2 lookaside cache is not present */
	    break;
	}
    return(size);
    }

/******************************************************************************
*
* sysL2InlineCacheSize() - Determine size of the L2 in-line cache.
*
* This function returns the size of the L2 in-line cache.  If no L2
* in-line cache is present, the size returned is zero so this function's
* return value can be used like a boolean to determine if the L2 in-line
* cache is actually present.
*
* RETURNS: Size of L2 in-line cache or zero if in-line cache not present.
*
* NOTE: Don't confuse the L2 in-line cache with the other possible type
* of cache, referred to as the "glance" or "lookaside" cache.
*/ 

LOCAL UINT sysL2InlineCacheSize()
    {
    STATUS size;

    if (CPU_TYPE != CPU_TYPE_750)
	return(0);	/* Not an Arthur chip so no in-line L2 cache */

    switch ( *SYS_REG_CCR & SYS_REG_CCR_P0STAT_MSK )
        {
        case SYS_REG_CCR_P0STAT_256:
 	    size = 0x40000;
 	    break;
        case SYS_REG_CCR_P0STAT_512:
 	    size = 0x80000;
 	    break;
        case SYS_REG_CCR_P0STAT_1024:
 	    size = 0x100000;
 	    break;
        default:
 	    size = 0;
 	    break;
        }
    return(size);
    }

/******************************************************************************
*
* sysL2InlineCacheSpd() - Determine size of the L2 in-line cache.
*
* This function returns the size of the L2 in-line cache.  If no L2
* in-line cache is present, the size returned is zero so this function's
* return value can be used like a boolean to determine if the L2 in-line
* cache is actually present.
*
* RETURNS: Size of L2 in-line cache or zero if in-line cache not present.
*
* NOTE: Don't confuse the L2 in-line cache with the other possible type
* of cache, referred to as the "glance" or "lookaside" cache.
*/ 

LOCAL UINT sysL2InlineCacheSpd(void)
   {
   UINT l2Spd;
   UINT i;

   if (sysL2InlineCacheSize() == 0)
      return(0);
   
   i = (*SYS_REG_MCR & SYS_REG_MCR_L2PLL_MSK) >> 8;

   l2Spd = ( ((sysGetMpuSpd() * 4) + (gen2FreqTable[i])) /
	      (gen2FreqTable[i] * 2) );

   return(l2Spd);
   }

/******************************************************************************
*
* nop - no op
*/ 

LOCAL int nop
    (
    int dummy
    )
    {
    return (dummy + 1);
    }

#endif	/* INCLUDE_CACHE_SUPPORT && INCLUDE_CACHE_L2 */