syscache.c

WINDRIVER MCP750 BSP

/* sysCache.c - secondary (L2) cache library for the Falcon */

/* Copyright 1984-1999 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01m,23may02,mil  Added initialization of L2 function hooks.
01l,25jan99,scb  Removed floating point arithmetic.
01k,29jul98,scb  Name change from "mv2600.h" to "mcpx750.h"
01d,14apr98,ms_  merged Motorola mv2700 support
01c,16oct97,scb  added MPC750 (Arthur) support.
01b,02jan97,wlf  doc: cleanup.
01a,14sep96,rhk  written.
*/

/*
DESCRIPTION

This library provides L2 cache support, and is derived from
code supplied by Motorola.

The driver only sets or clears one bit at a time in the System
External Cache Control register, per the Genesis 2 programming
guide.

The flush bit in the System External Cache Control register should
not be used.

*/

/* includes */

#include "vxWorks.h"
#include "mcpx750.h"

#if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L2)

/* forward declarations */

STATUS           sysL2CacheInit (void);
LOCAL STATUS     sysL2LookasideCacheInit (void);
LOCAL STATUS     sysL2InlineCacheInit (void);

void             sysL2CacheEnable (void);
LOCAL void       sysL2LookasideCacheEnable (void);
LOCAL void       sysL2InlineCacheEnable (void);

void             sysL2CacheDisable (void);
LOCAL void       sysL2LookasideCacheDisable (void);
LOCAL void       sysL2InlineCacheDisable (void);

void             sysL2CacheFlush (void);
LOCAL void       sysL2InlineCacheFlush (void);

void             sysL2CacheInvFunc (void);
LOCAL void       sysL2InlineCacheInvFunc (void);

LOCAL UINT       sysL2LookasideCacheSize (void);
LOCAL UINT       sysL2InlineCacheSize (void);
LOCAL UINT	 sysL2InlineCacheSpd (void);
LOCAL int	 nop (int);

/* externals */

IMPORT UINT sysL2crGet (void);
IMPORT void sysL2crPut (UINT regVal);
IMPORT UINT sysGetMpuSpd (void);

IMPORT void sysMaxL2Disable(void);
IMPORT void sysMaxL2InvFunc(void);
IMPORT void sysMaxL2Flush(void);

IMPORT VOIDFUNCPTR _pSysL2CacheInvFunc;
IMPORT VOIDFUNCPTR _pSysL2CacheEnable;
IMPORT VOIDFUNCPTR _pSysL2CacheFlush;
IMPORT VOIDFUNCPTR _pSysL2CacheDisable;

LOCAL UINT gen2ConvTable[] =
    {
    0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x0, 0x0, 0x0,
    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
    };

LOCAL UINT gen2FreqTable[] =
    {
    2, 2, 3, 4, 5, 6, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2 
    };

/******************************************************************************
*
* sysL2CacheInit - initialize the L2 cache 
*
* This routine initializes and enables L2 cache support.  
*
* RETURNS: OK, or ERROR if cache is not present or not supported.
*
*/ 

STATUS sysL2CacheInit (void)
    {

    STATUS status = OK;
    /* check for presence of L2 cache */

#if FALSE       /* lookasidecache not on MCP750 */
    if (sysL2LookasideCacheSize() != 0)
	status |= sysL2LookasideCacheInit();
#endif FALSE

    if (sysL2InlineCacheSize() != 0)
	status |= sysL2InlineCacheInit();

    if (status == OK)
        {

        /* hook up the L2 functions */

        _pSysL2CacheEnable  = sysL2CacheEnable;
        _pSysL2CacheFlush   = sysL2CacheFlush;
        _pSysL2CacheDisable = sysL2CacheDisable;
        _pSysL2CacheInvFunc = sysL2CacheInvFunc;

        }

    return (status);
    }

/******************************************************************************
*
* sysL2LookasideCacheInit - initialize the L2 lookaside cache 
*
* This routine initializes and enables L2 lookaside cache support.
*
* RETURNS: OK, or ERROR if cache is not present or not supported.
*
*/ 

LOCAL STATUS sysL2LookasideCacheInit(void)
    {

    /* check for presence of L2 cache */

    if (sysL2LookasideCacheSize() == 0)
        return(ERROR);		/* No L2 cache to init */

    /* disable the L2 cache, and invalidate the tags */
    sysL2LookasideCacheDisable ();

    /* Enable the L2 cache(s) */
    sysL2LookasideCacheEnable();

    return (OK);
    }

/******************************************************************************
*
* sysL2InlineCacheInit - initialize the L2 in-line cache.
*
* This routine initializes and enables L2 in-line cache support.
*
* RETURNS: OK, or ERROR if cache is not present or not supported.
*
*/ 

LOCAL STATUS sysL2InlineCacheInit(void)
    {
    UINT l2CacheSize;
    UINT l2crVal;
    UINT i;

    /* check for presence of L2 cache */

    if ((l2CacheSize = sysL2InlineCacheSize()) == 0)
        return(ERROR);		/* No L2 cache to init */

    /* Initialize RAM type, output hold, differential clock */

    switch ( (*SYS_REG_MCR) & SYS_REG_MCR_L2TYPE_MSK )
	{
	case SYS_REG_MCR_L2TYPE_LWP:  /* Late Write, with Parity */
	case SYS_REG_MCR_L2TYPE_LWNP: /* Late Write, without Parity */
	    l2crVal = 0x01814000;     /* L2PE  = No parity enable      
				       * L2RAM = Pipe reg reg sync burst
				       * L2OH  = 1.0ns
				       * L2DF  = Diff clock
				       */
	    break;
	case SYS_REG_MCR_L2TYPE_BP:   /* Burst with parity */
	case SYS_REG_MCR_L2TYPE_BNP:  /* Burst, without Parity */
	    l2crVal = 0x01000000;     /* L2PE  = No parity enable      
				       * L2RAM = Flow thru reg buf sync burst
				       * L2OH  = 0.5ns
				       * L2DF  = Nondiff clock
				       */
	    break;
	default:
	    l2crVal = 0;
	    break;
	}

    /* Initialize the L2 clock ratio */

    i = (*SYS_REG_MCR & SYS_REG_MCR_L2PLL_MSK) >> 8;
    l2crVal |= gen2ConvTable[i] << 25;

    if (sysL2InlineCacheSpd() < 100)
        l2crVal |= MPC750_L2CR_SL;

    /* Set the Cache size */

    switch (l2CacheSize)
	{
	case 0x00040000:
	    l2crVal |= MPC750_L2CR_256K;
	    break;
	case 0x00080000:
	    l2crVal |= MPC750_L2CR_512K;
	    break;
	case 0x00100000:
	    l2crVal |= MPC750_L2CR_1024K;
	    break;
	}

    /* Write out the L2 cache control register */

    sysL2crPut(l2crVal);

    /* Invalidate the L2 cache */

    l2crVal |= MPC750_L2CR_I;
    sysL2crPut(l2crVal);
    while (sysL2crGet() & MPC750_L2CR_IP)
	;
    l2crVal &= ~MPC750_L2CR_I;
    sysL2crPut(l2crVal);

    /* Enable the L2 cache */
    sysL2InlineCacheEnable();

    return (OK);
    }

/******************************************************************************
*
* sysL2CacheEnable - enable the L2 cache(s)
*
* RETURNS: void
*
*/

void sysL2CacheEnable (void)
    {
    UINT cacheSize;

#if FALSE       /* lookasidecache not on MCP750 */
    if ((cacheSize = sysL2LookasideCacheSize()) != 0)
        {
        sysL2LookasideCacheEnable();
        }
#endif

    if ((cacheSize = sysL2InlineCacheSize()) != 0)
        {
        sysL2InlineCacheEnable();
        }
    }

/******************************************************************************
*
* sysL2LookasideCacheEnable - enable the L2 lookaside cache
* 
* RETURNS: void
*
*/ 

LOCAL void sysL2LookasideCacheEnable (void)
    {
    unsigned char regVal;
 
    if (sysL2LookasideCacheSize() == 0)
	return;                   /* Return if no L2 Lookaside cache present */

    /* make sure L2 is already disabled */
    regVal = ((*SYS_REG_SXCCR) & L2_ENABLE);
    if (regVal == 0)
        *SYS_REG_SXCCR |= L2_ENABLE;
    }

/******************************************************************************
*
* sysL2InlineCacheEnable - enable the L2 in-line cache
* 
* RETURNS: void
*
*/ 

LOCAL void sysL2InlineCacheEnable (void)
    {
    UINT l2crVal;
 
    if (sysL2InlineCacheSize() == 0)
	return;

    /* make sure L2 is already disabled */
    if ( ((l2crVal = sysL2crGet()) & MPC750_L2CR_E) == 0)
	{
        l2crVal |= MPC750_L2CR_E;
	sysL2crPut(l2crVal);
	}
    }

/******************************************************************************