syslib.c

WINDRIVER SBC405 BSP

/* sysLib.c - Wind River SBC405GP system-dependent routines */

/* Copyright 1984-2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01g,12sep02,pch  SPR 80226: defer connecting sysUicIntHandler until sysHwInit2
01f,26jun02,pch  SPR 73650 & 76704: clean up refs to processor revisions
01e,24jan02,pch  Fix Diab warnings
01d,18jan02,g_h  Change MAL_DCR_BASE to MAL0_DCR_BASE
01c,14jan02,pch  Remove reference to unsupported PVR_405GP_RA
01b,17sep01,g_h  update to reflect the changes done in T2CP4
01a,22apr01,g_h  created from Walnut version 01j.
*/

/*
DESCRIPTION
This library provides board-specific routines.   The chip drivers included are:

    uicIntr.c       - on-chip Universal Interrupt Controller library
    ppc405Timer     - System timer, Timestamp & Aux clock driver
    ibmEmacEnd.obj  - IBM EMAC Ethernet driver END style


INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "cacheLib.h"
#include "asm.h"
#include "vme.h"
#include "iv.h"
#include "esf.h"
#include "ioLib.h"
#include "sysLib.h"
#include "config.h"
#include "memLib.h"
#include "excLib.h"
#include "logLib.h"
#include "vxLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "private/vmLibP.h"
#include "ppc405GP.h"
#include "wrSbc405gp.h"

/* externals */

IMPORT STATUS   excIntConnectTimer (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
IMPORT void     excIntHandle (void);
IMPORT UINT32   sysSTRAPGet (void);
IMPORT UINT32   ppc405IccrVal; /* cachability state for instruction */
IMPORT UINT32   ppc405DccrVal; /* cachability state for data */

/* globals */

int      sysBus;                       /* system bus type (VME_BUS, etc) */
int      sysCpu      = CPU;            /* system CPU type (PPC405GP) */
char   * sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char   * sysExcMsg   = EXC_MSG_ADRS;   /* catastrophic message area */
int      sysFlags;                     /* boot flags */
char     sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char     sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
int      sysTimerClkFreq;              /* Timer clock frequency             */
SYS_INFO systemInfo;                   /* PLL and system frequencies        */
int	 sysProcNum;			/* processor number of this CPU */

/*
 * The following variables specify the cache line size and the number of
 * cache lines for the 405GP. These are used by the architecture cache
 * libraries.
 */
const int ppc405ICACHE_LINE_NUM  = _ICACHE_LINE_NUM_405GP; /* no. of lines in ICACHE */
const int ppc405DCACHE_LINE_NUM  = _DCACHE_LINE_NUM_405GP; /* no. of lines in DCACHE */
const int ppc405CACHE_ALIGN_SIZE = _CACHE_ALIGN_SIZE;	   /* cache line size */

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * IO space and local PROM/FLASH are set here.
 *
 * PTEs are held in a 2-level page table. There is one Level 1 page table
 * and several Level 2 page tables. The size of the Level 1 table is 4K
 * and the size of each Level 2 page table is 8K. Each Level 2 table can
 * map upto 4MB of contiguous memory space.
 *
 * Calculating size of page table required:
 * =======================================
 * For the following memory map we can calculate the page table size
 * required as follows:
 *
 *	Memory Area             Size        # of Level 2 pages
 *	===========             ====        ==================
 *	1.  Local Memory	32MB        8
 *	2.  PCI Memory		64MB        16
 *	3.  PCI IO Regn 1	64K         1
 * 	4.  PCI IO Regn 2	1MB         1
 *	5.  PCI CFG             4K          1
 * 	6.  PCI IACK		4K          0 @
 *	7.  PP Bridge		4K          1
 * 	8.  UART IO Space	4K          0 @
 *	9.  Flash               16MB        4
 *	@ - included in previous L2 page
 *
 *	Total # of L2 pages =               32
 *	Total Memory Required for page table = 32 * 8 + 4 = 260 K.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    LOCAL_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },
#ifdef INCLUDE_PCI
    {
    (void *) PCI_MEMORY_START,
    (void *) PCI_MEMORY_START,
    PCI_MEMORY_MAP_END - PCI_MEMORY_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) PLB_PCI_IO_REGION_1_START,
    (void *) PLB_PCI_IO_REGION_1_START,
    PLB_PCI_IO_REGION_1_END - PLB_PCI_IO_REGION_1_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) PLB_PCI_IO_REGION_2_START,
    (void *) PLB_PCI_IO_REGION_2_START,
    PLB_PCI_IO_REGION_2_MAP_END - PLB_PCI_IO_REGION_2_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) PCI_CFGADDR,
    (void *) PCI_CFGADDR,
    PCI_CFGEND - PCI_CFGADDR + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) PCI_INTERRUPT_ACK,
    (void *) PCI_INTERRUPT_ACK,
    PCI_INTERRUPT_ACK_END - PCI_INTERRUPT_ACK + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) PP_BRIDGE_CR,
    (void *) PP_BRIDGE_CR,
    PP_BRIDGE_CR_END - PP_BRIDGE_CR + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },
#endif /* INCLUDE_PCI */
    {
    (void *) UART_MEMORY_START,
    (void *) UART_MEMORY_START,
    UART_MEMORY_END - UART_MEMORY_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },
#ifdef INCLUDE_WR_FPGA_CARD
#ifdef WR_FPGA_CARD_ON_LOCAL_BUS
    {
    (void *) WR_FPGA_SSRAM_ADRS,
    (void *) WR_FPGA_SSRAM_ADRS,
    WR_FPGA_SSRAM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    },

    {
    (void *) WR_FPGA_EPLD_ADRS,
    (void *) WR_FPGA_EPLD_ADRS,
    WR_FPGA_EPLD_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    }
#endif /* WR_FPGA_CARD_ON_LOCAL_BUS */
#endif /* INCLUDE_WR_FPGA_CARD */
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

/* forward declarations */

STATUS sysInfoGet (SYS_INFO * sysInfo, int verbose);
void   sysLocalDelay (UINT32 ms_delay);
void   sysCpuCheck (void);
UCHAR  sysPciInByte (ULONG address);
void   sysPciOutByte (ULONG address, UCHAR data);
UINT16 sysPciInWord (ULONG address);
void   sysPciOutWord (ULONG address, UINT16 data);
UINT   sysPciInLong (ULONG address);
void   sysPciOutLong (ULONG address, UINT data);

/* locals */

LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG;
/* Make sure this is big enough for the sprintf() in sysCpuCheck() */
LOCAL char wrongCpuPvr[] = "[PVR=xxxxxxxx]!\r\n";

#ifdef DOC
#define INCLUDE_TIMESTAMP
#endif

/* BSP Drivers */

/* Source Drivers */

#if (NV_RAM_SIZE != NONE)
#include "sysNvRam.c"
#else
#include "mem/nullNvRam.c"
#endif /* (NV_RAM_SIZE != NONE) */

#include "vme/nullVme.c"
#include "uicIntr.c"                    /* UIC interrupt library */
#include "ppc405Timer.c"                /* ppc405 timer driver */
#include "sysSerial.c"

#ifdef INCLUDE_WR_FPGA_CARD
#include "sysProteus.c"
#endif /* INCLUDE_WR_FPGA_CARD */

#ifdef INCLUDE_PCI
#include "pci/pciConfigLib.c"
#include "pci/pciConfigShow.c"
#  ifdef INCLUDE_PCI_AUTOCONF
#  include "sysPciAutoConfig.c"
#  endif /* INCLUDE_PCI_AUTOCONF */
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif /* INCLUDE_VWARE_LAUNCH */

#ifdef INCLUDE_NETWORK
#include "sysNet.c"
#  ifdef INCLUDE_FEI82557END
#  include "sysFei82557End.c"
#  endif /* INCLUDE_FEI82557END */
#  ifdef INCLUDE_EMAC_NETWORK
#  include "malLib.c"
#  include "sysIbmEmacEnd.c"
#endif /* INCLUDE_EMAC_NETWORK */
#endif /* INCLUDE_NETWORK */

/**************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string "WindRiver. SBC405GP - IBM PowerPC Rev. x".  Where
* x is either 1 or 2.
*/

char * sysModel
    (
    void
    )
    {
    switch (vxPvrGet ())
	{
	case PVR_405GP_RB:
	    return ("IBM PowerPC 405GP Rev B (Not supported) - WindRiver. SBC405GP"); /* Not supported */
	case PVR_405GP_RC:
	    return ("IBM PowerPC 405GP Rev C (Not supported) - WindRiver. SBC405GP"); /* Not supported */
	case PVR_405GP_RD:
	    return ("IBM PowerPC 405GP Rev D - WindRiver. SBC405GP");
	case PVR_405GP_RE:
	    return ("IBM PowerPC 405GP Rev E - WindRiver. SBC405GP");
	default:
	    return ("Unknown processor");
	}
    }

/**************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.2/0.  BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev
    (
    void
    )
    {
    return (BSP_VERSION BSP_REV);
    }

/*******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various features of the Wind River SBC405GP board. This
* routine clears and turns off the external interrupts.  It is called from
* usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user application.
*
* RETURNS: N/A
*/

void sysHwInit
    (
    void
    )
    {

#ifdef INCLUDE_VWARE_LAUNCH
    char vwareMacAdrs[VWARE_MAC_ADRS_LEN];
#endif /* INCLUDE_VWARE_LAUNCH */

    /* Validate CPU type */

    sysCpuCheck ();

    /* Fill in global system information structure */

    sysInfoGet (&systemInfo, FALSE);

    /* Set the 405 Exception Vector Prefix Register */

    vxEvprSet (SBC405GP_EVPR_VAL);

    /* Interrupt system initialization */

    sysUicIntrInit ();

    /*
     * Initialize timer clock mode determine the timer clock frequency
     */

#ifdef TIMER_CLOCK_EXTERNAL
    /*
     * Set the external timer clock bit in Chip Control Reg 1.
     */

    sysDcrCr1Set (sysDcrCr1Get () | CR1_EXT_TIMER_EN);
    sysTimerClkFreq = EXT_TIMER_CLK_FREQ;
#else  /* Timers run at the processor clock speed */
    sysTimerClkFreq = systemInfo.freqProcessor;
#endif /* TIMER_CLOCK_EXTERNAL */

#ifdef INCLUDE_EMAC_NETWORK
    malReset(MAL0_DCR_BASE);
#endif /* INCLUDE_EMAC_NETWORK */

    /* Initialize the PCI configuration library, and the 405GP PCI bridge */

#ifdef INCLUDE_PCI
    pciConfigLibInit (PCI_MECHANISM_0, (ULONG)sysPciConfigRead, (ULONG)sysPciConfigWrite, 0);
    sysPciHostBridgeInit ();
#endif /* INCLUDE_PCI */

    /* Perform auto-configuration of devices on the PCI bus  */

#ifdef INCLUDE_PCI_AUTOCONF
    sysPciAutoConfig ();
#endif /* INCLUDE_PCI_AUTOCONF */

#ifdef INCLUDE_NETWORK
    sysNetHwInit ();             /* network interface */
#endif /* INCLUDE_NETWORK */

#ifdef  FORCE_DEFAULT_BOOT_LINE
    strncpy (sysBootLine,DEFAULT_BOOT_LINE,strlen(DEFAULT_BOOT_LINE)+1);
#else
#  ifdef INCLUDE_VWARE_LAUNCH
#    ifdef INCLUDE_EMAC_NETWORK
        if (sysVwareBuildBootLine ((char*)&vwareMacAdrs))
            {
            sysEnetAddrSet (vwareMacAdrs[5],
		            vwareMacAdrs[4],
			    vwareMacAdrs[3],
			    vwareMacAdrs[2],
			    vwareMacAdrs[1],
			    vwareMacAdrs[0]);
             }
#    else /* INCLUDE_EMAC_NETWORK */
        sysVwareBuildBootLine (0);
#    endif /* INCLUDE_EMAC_NETWORK */

#  endif /* INCLUDE_VWARE_LAUNCH */
#endif /* FORCE_DEFAULT_BOOT_LINE */

    /* initialize the serial driver(s) */

#ifdef INCLUDE_SIO
    sysSerialHwInit ();
#endif /* INCLUDE_SIO */

    /*
     * ppc405IccrVal and ppc405DccrVal define respectively the cachability
     * state of the total effective adress space at a 128 MB granularity
     * for instruction and data.  See wrSbc405gp.h
     */

#ifdef INCLUDE_CACHE_SUPPORT
    ppc405IccrVal = SBC405GP_ICCR_VAL;
    ppc405DccrVal = SBC405GP_DCCR_VAL;
#endif /* INCLUDE_CACHE_SUPPORT */

    }

/**************************************************************************
*
* sysHwInit2 - initialize additional system hardware
*
* This routine connects system interrupts and configures any required features
* not configured by sysHwInit().
*
* RETURNS: N/A
*/

void sysHwInit2
    (
    void
    )
    {
    static BOOL configured = FALSE;

    if (!configured)
        {
	excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_INTR, sysUicIntHandler);
	excIntCrtConnect ((VOIDFUNCPTR *) _EXC_OFF_CRTL, sysUicIntHandler);

        /* connect system clock interrupt */

	excIntConnectTimer ((VOIDFUNCPTR *) _EXC_OFF_PIT,
			    (VOIDFUNCPTR) sysClkInt);

#ifdef INCLUDE_AUX_CLK
        /* connect auxiliary clock interrupt */

	excIntConnectTimer ((VOIDFUNCPTR *) _EXC_OFF_FIT,
			    (VOIDFUNCPTR) sysAuxClkInt);
#endif /* INCLUDE_AUX_CLK */

#ifdef INCLUDE_NETWORK
        sysNetHwInit2 ();       /* network interface */
#endif /* INCLUDE_NETWORK */

#ifdef INCLUDE_SIO
        /* connect serial interrupts */

        sysSerialHwInit2();
#endif /* INCLUDE_SIO */

        configured = TRUE;
        }
    }

/**************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,