mallib.h

WINDRIVER SBC405 BSP

/* malLib.h - IBM Memory Access Layer (MAL) library header */

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   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
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   licensors will be responsible for any consequences resulting from the use
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   COPYRIGHT   I B M   CORPORATION 2000
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/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,16may01,mcg  common driver for walnut (405GP), cedar (NPe405x)
01b,15jan00,mcg  added alignment requirement for buffer descriptor rings
01a,18oct99,mcg  created
*/

/*
This file contains constants for the IBM Memory Access Layer core.
*/

#ifndef INCmalLibh
#define INCmalLibh

#ifdef __cplusplus
extern "C" {
#endif

#define MAL_NUM_TYPES  2
#define MAL_TX_TYPE    0
#define MAL_RX_TYPE    1
#define MAL_MAX_CHANNELS 32    /* 32 for receive, 32 for transmit */

/*
 * Reduced configurations of MAL are used for chips with fewer communication
 * cores inside.
 */

#define MAL_NO_INTS       0x00000000
#define MAL_EOB_INT_EN    0x00000001
#define MAL_DE_INT_EN     0x00000002
#define MAL_SERR_INT_EN   0x00000004

#define MAL_MAX_DESC            256            /* max descriptors per channel */
#define MAL_MAX_DESC_TBL_SIZE  (MAL_MAX_DESC * sizeof(MAL_BD))
#define MAL_DESC_REQ_ALIGN     (512*1024)      /* 512KB                       */


/* MAL Channel structure */

typedef struct
    {
    UINT         channelType;       /* TX_TYPE or RX_TYPE                     */
    UINT         channelNum;        /* channel number (0 through 31)          */
    UINT         bufferSizeRX;      /* receive buffer size if an RX channel   */
    UINT         channelIntMask;    /* interrupt mask for this channel        */
    VOIDFUNCPTR  functionEOB;       /* function for EOB int on this channel   */
    UINT         parmEOB;           /* parameter for the above function       */
    VOIDFUNCPTR  functionDescErr;   /* function for DE int on this channel    */
    UINT         parmDescErr;       /* parameter for the above function       */
    VOIDFUNCPTR  functionSERR;      /* function for MAL SERR int for this chn */
    UINT         parmSERR;          /* parameter for the above function       */
    } MAL_CHANNEL;

/*
 * MAL initialization structure.  This information is passed to the MAL driver
 * in malInit().
 */

typedef struct
    {
    UINT dcrBaseReg;
    UINT validChannels[MAL_NUM_TYPES];
    UINT intLvlTxeob;
    UINT intVecTxeob;
    UINT intLvlRxeob;
    UINT intVecRxeob;
    UINT intLvlTxde;
    UINT intVecTxde;
    UINT intLvlRxde;
    UINT intVecRxde;
    UINT intLvlSerr;
    UINT intVecSerr;
    } MAL_INIT;

/*
 *  MAL driver control stucture.
 */

typedef struct
    {
    MAL_INIT  malInit;
    char *descTablesAlloc;
    char *descTables;
    UINT malInitializedChannels[MAL_NUM_TYPES];
    MAL_CHANNEL malChannelArray[MAL_NUM_TYPES][MAL_MAX_CHANNELS];
    } MAL_DATA;


/*
 * MAL Buffer Descriptor Structure.  The same structure is used for both
 * Transmit and Receive channels.
 */
typedef struct
    {
    USHORT   statusControl;              /* Shared between MAL and comm core */
    USHORT   dataLen;                    /* Buffer byte count                */
    char   * bufferAdrs;                 /* Buffer address                   */
    } MAL_BD;


/*
 * The status/control bits in the MAL buffer descriptor structure have different
 * meaning if the descriptor is used by a TX channel versus an RX channel.
 * Bits 0:5 are used to convey MAL control/status.  Bits 6:15 are
 * used to convey the communication core's (EMAC for example) control/status.
 */

/* MAL TX Descriptor Control/Status bits */
#define MAL_TX_CTRL_READY     0x8000           /* Packet ready to transmit    */
#define MAL_TX_CTRL_WRAP      0x4000           /* Last descriptor in the ring */
#define MAL_TX_CTRL_CM        0x2000
#define MAL_TX_CTRL_LAST      0x1000           /* Last buffer for this packet */
#define MAL_TX_CTRL_INTR      0x0400           /* Intr when packet TX complete*/

/* MAL RX Descriptor Control/Status bits */
#define MAL_RX_CTRL_EMPTY     0x8000           /* Buffer empty, ready to RX   */
#define MAL_RX_CTRL_WRAP      0x4000           /* Last descriptor in the ring */
#define MAL_RX_CTRL_CM        0x2000
#define MAL_RX_CTRL_LAST      0x1000           /* Last buffer for this packet */
#define MAL_RX_CTRL_FIRST     0x0800           /* 1st buffer for this packet  */
#define MAL_RX_CTRL_INTR      0x0400           /* Intr when packet RX complete*/

/* Masks */
#define MAL_MAL_CTRL_BITS     0xFC00           /* All descriptor bits for MAL */
#define MAL_COMMAC_CTRL_BITS  0x03FF           /* All descriptor bits for the */
                                               /* communications core         */

#define MAL_RX_ONE_BUFFER     (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)


/* External functions */

void   malReset(UINT dcrBaseReg);
MAL_DATA * malInit(MAL_INIT *pMalInit);
STATUS malChannelInit(MAL_DATA *pMalData, MAL_CHANNEL *pChannel);
STATUS malChannelDelete(MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS malChannelActivate(MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS malChannelStop(MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS malChannelIntMaskGet(MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT * intMask);
STATUS malChannelIntMaskSet(MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT intMask);
STATUS malChannelDescTblPtrGet(MAL_DATA *pMalData, UINT channelType, UINT channelNum,
                               MAL_BD ** descTblAdrs);
STATUS malShutDown(MAL_DATA *pMalData);

#ifdef __cplusplus
}
#endif

#endif  /* INCmalLibh */