wrsbc405gp.h

WINDRIVER SBC405 BSP

/* wrSbc405gp.h - Wind River SBC405GP eval board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,19apr02,gjc  The FIT is based on the cpu clock not the system clock.
01a,22apr01,gh   created from walnut.h rev 01c
*/

/*
This file contains I/O addresses and related constants for the
wind River SBC405GP BSP.
*/

#ifndef __INCwrSbc405gph
#define __INCwrSbc405gph

#ifdef __cplusplus
extern "C" {
#endif

/* On board device I/O adress */

#define FLASH_BASE_ADRS		       0xFF000000
#define FLASH_SIZE		       0x01000000

#ifdef  INCLUDE_WR_FPGA_CARD
#define WR_FPGA_SSRAM_ADRS             0x70000000
#define WR_FPGA_SSRAM_SIZE             0x01000000
#define WR_FPGA_EPLD_ADRS              0xF0000000
#define WR_FPGA_EPLD_SIZE              0x00001000
#endif  /* INCLUDE_WR_FPGA_CARD */

/* NvRam on FLASH macros */

#define ONE_K			       1024
#define FLASH_SECTOR_SIZE	       (128 * ONE_K * 2)

/* SBC405GP clock frequencies */

#define ONE_BILLION		        (1000 * 1000 * 1000)
#define SYS_CLK_FREQ		        33333333 /* 33.333333 MHz */
#define SYS_PLL_DIVIDE                  6
#define EXT_TIMER_CLK_FREQ	        (SYS_CLK_FREQ)
#define CPU_AUX_CLK_FREQ                (SYS_CLK_FREQ*SYS_PLL_DIVIDE)
#define EXT_SER_CLK_FREQ	        3686400	/* 3.6864 MHz dedicated clk  */

/*
 * Exception Vector Prefix Register value.  Exception vectors will be located
 * at the start of SDRAM.
 */

#define SBC405GP_EVPR_VAL               0x00000000

#define VEC_BASE	                (char *)0

/*
 * Initial values for UIC interrupt controller polarity, triggering, and
 * critical vs. non-critical.
 */

#define UIC_INTR_POLARITY              0xFFFFFFF0
#define UIC_INTR_TRIGGER               0x00000000
#define UIC_INTR_CRITICAL              0x00000000

/*
 * The address of the PHY attached to the MII interface of EMAC.
 */

#define EMAC_PHY_ADRS                  1

/*
 * SBC405GP_ICCR_VAL and SBC405GP_DCCR_VAL define the cachability
 * state of the total effective adress space at a 128 MB granularity
 * for instruction and data.
 * By default memory spaces 0x00000000-0x07ffffff and 0xf8000000-0xfffffffff
 * are set as cached. The rest of the effective adress space is programmed
 * as non-cached.
 * this can be changed here, according to the memory board mapping.
 */

#define SBC405GP_ICCR_VAL              _PPC405_ICCR_DEFAULT_VAL
#define SBC405GP_DCCR_VAL              _PPC405_DCCR_DEFAULT_VAL

/*
 * PCI
 */

#ifdef INCLUDE_PCI

#define SBC405GP_NUM_PCI_SLOTS         1

#define INTEL21154PCI_BRIDGE           1
#define PPC405PCI_BRIDGE               0

#define EXPANTION_BOARD_PCI_SLOT_J26   12
#define EXPANTION_BOARD_PCI_SLOT_J25   13
#define EXPANTION_BOARD_PCI_SLOT_J24   14
#define EXPANTION_BOARD_cPCI_SLOT_J22  15 

#define SBC405GP_PCI_INTA_IRQ          28
#define PCI_EXPAND_PCI_INTA_IRQ        28
#define PCI_EXPAND_PCI_INTB_IRQ        29
#define PCI_EXPAND_PCI_INTC_IRQ        30
#define PCI_EXPAND_PCI_INTD_IRQ        31

/* Translate PCI addresses to virtual addresses (master windows) */

#define PCI_MEMIO2LOCAL(x)             (x)
#define LOCAL2PCI_MEMIO(x)             (x)

/*
 * Routines for reading or writing PCI I/O or Memory space. These routines are
 * written in assembler and use byte swapping load/store instructions.
 */
#ifndef _ASMLANGUAGE

#define PCI_IN_BYTE(x)                 sysPciInByte (x)
#define PCI_IN_WORD(x)                 sysPciInWord (x)
#define PCI_IN_LONG(x)                 sysPciInLong (x)
#define PCI_OUT_BYTE(x,y)              sysPciOutByte (x,y)
#define PCI_OUT_WORD(x,y)              sysPciOutWord (x,y)
#define PCI_OUT_LONG(x,y)              sysPciOutLong (x,y)

#endif /* _ASMLANGUAGE */

/*
 * PCI Autoconfig Configuration Defines - Mandatory stuff that must be defined in
 * order to use vWare's PCI Autoconfig.
 */

#define PCI_ADDRESS_REGISTER           0xEEC00000 /* PCI Address Register		  */
#define PCI_DATA_REGISTER              0xEEC00004 /* PCI Data Register		          */
#define PCI_MEM_ADRS                   0x00000000
#define PCI_MEM_SIZE                   0x00000000
#define PCI_MEMIO_ADRS	               0x80000000 /* PCI Auto Config Memory Start Address */
#define PCI_MEMIO_SIZE		       0x68000000 /* PCI Auto Config Memory Size	  */
#define PCI_IO_ADRS		       0xE8800000 /* PCI Auto Config IO Start Address	  */
#define PCI_IO_SIZE		       0x06400000 /* PCI Auto Config IO Size	          */
#define PCI_ISA_IO_ADRS	               0xE8000000
#define PCI_ISA_IO_SIZE	               (0x1000)

#define PCICMD                         0x04
#define BM_EN                          0x0004
#define MEM_EN                         0x0002
#define PCI_ASYNC_MODE_EN              0x00001000

#define PCIBASEADDR1                   0x14
#define PCIBASEADDR2                   0x18
#define PCIBRDGOPT1                    0x4A
#define PCIBRDGOPT2                    0x60

#endif /* INCLUDE_PCI */

/* Clock Parameters */

#ifdef  TIMER_CLOCK_EXTERNAL
#define AUX_CLK_RATE_MIN               (EXT_TIMER_CLK_FREQ / (1 << 21) ) /* min auxiliary clock rate */
#define AUX_CLK_RATE_MAX               (EXT_TIMER_CLK_FREQ / (1 << 9)  ) /* max auxiliary clock rate */
#define AUX_CLK_RATE_DEFAULT           (EXT_TIMER_CLK_FREQ / (1 << 17) )
#else
#define AUX_CLK_RATE_MIN               (CPU_AUX_CLK_FREQ / (1 << 21) )       /* min auxiliary clock rate */
#define AUX_CLK_RATE_MAX               (CPU_AUX_CLK_FREQ / (1 << 9)  )       /* max auxiliary clock rate */
#define AUX_CLK_RATE_DEFAULT           (CPU_AUX_CLK_FREQ / (1 << 17) )
#endif  /* TIMER_CLOCK_EXTERNAL */

#define SYS_CLK_RATE_MIN               3    /* minimum system clock rate   */
#define SYS_CLK_RATE_MAX               5000 /* maximum system clock rate   */

#define WDT_RATE_MIN                   1    /* minimum watchdog timer rate */
#define WDT_RATE_MAX                   5000 /* maximum watchdog timer rate */

/* Define CPU type and number of Serial channels  */

#define BUS                            BUS_TYPE_PCI /* PCI bus unterface       */
#define CPU                            PPC405       /* CPU type                  */
#define N_SIO_CHANNELS                 2            /* No. serial I/O channels */

#ifndef _ASMLANGUAGE

/*
 * System information structure.  It is used to get information about the
 * 405GP PLL and operating frequencies.
 */

typedef struct
    {
    UINT32  pllFwdDiv;
    UINT32  pllFbkDiv;
    UINT32  pllPlbDiv;
    UINT32  pllPciDiv;
    UINT32  pllExtBusDiv;
    UINT32  pllOpbDiv;
    UINT32  freqVCOMhz;             /* in MHz                          */
    UINT32  freqProcessor;
    UINT32  freqPLB;
    UINT32  freqPCI;
    UINT32  pciIntArbEn;            /* Internal PCI arbiter is enabled */
    UINT32  pciClkSync;             /* PCI clock is synchronous        */
    } SYS_INFO;

#endif /* _ASMLANGUAGE */

/* generic macros */

#undef  EIEIO
#define EIEIO                          WRS_ASM("	eieio")

#undef  EIEIO_SYNC
#define EIEIO_SYNC                     WRS_ASM("	eieio;	sync")

#undef  SYNC
#define SYNC                           WRS_ASM("	sync")

#ifdef __cplusplus
}
#endif

#endif  /* __INCwrSbc405gph */