ibmemacend.h

WINDRIVER SBC405 BSP

/* ibmEmacEnd.h - END based IBM EMAC Ethernet header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

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   licensors will be responsible for any consequences resulting from the use
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   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/*
modification history
--------------------
01m,06nov01,alr  fix (SPR 71487) ibmEmacEnd: driver may instruct MUX to block
		 (EMAC_TX_BLOCKED/END_ERR_BLOCK) but never call muxTxRestart
01l,18oct01,mcg  Polled mode fixes, added OPB speed variables to main struct.
01k,20aug01,kab  Change ibmEmac to emac - max 4 letter boot dev in DHCP, other
01j,25jul01,pmr  added macro to control memory allocation for loaning buffers
01i,10may01,mcg  extensive changes to driver to remove data cache coherency
                 code, add support for both TX channels, add full-duplex flow
                 control support.  405 kernel must be used.
01h,09may01,pmr  changed ENET_HDR_REAL_SIZ to SIZEOF_ETHERHEADER.
01g,29nov00,s_m  changes from ibm
01f,02nov00,mcg  added semMutexRX to device structure
01e,05jul00,mcg  added phyAnlpr to device structure
01d,15may00,mcg  register name updates to match 405GP User Manual
01c,03mar00 mcg  Added bit fields. TX and RX descriptor queues to 64 entries
01b,07dec99 mcg  Increased default TX and RX descriptor queues to 128 entries
01a,11oct99,mcg  created.
*/

#ifndef __INCibmEmacEndh
#define __INCibmEmacEndh

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "end.h"
#include "cacheLib.h"
#include "malLib.h"
#include "wdLib.h"


/* Change to TRUE for debug messages */

#if FALSE
#define DRV_DEBUG
#endif

/* Define flags for DRV_LOG message filtering */

#ifdef  DRV_DEBUG
#include "logLib.h"
#define DRV_DEBUG_RX            0x0001
#define DRV_DEBUG_TX            0x0002
#define DRV_DEBUG_INT           0x0004
#define DRV_DEBUG_POLL          0x0008
#define DRV_DEBUG_POLL_RX       0x0010
#define DRV_DEBUG_POLL_TX       0x0020
#define DRV_DEBUG_LOAD          0x0040
#define DRV_DEBUG_IOCTL         0x0080
#define DRV_DEBUG_RESET         0x0100
#define DRV_DEBUG_MCAST         0x0200
#define DRV_DEBUG_ERROR         0x0400
#define DRV_DEBUG_INFO          0x0800
#define DRV_DEBUG_START         0x1000
#define DRV_DEBUG_SEND          0x2000
#define DRV_DEBUG_RECV          0x4000
#define DRV_DEBUG_ENET_INT      0x8000
#define DRV_DEBUG_STATUS       0x10000
#define DRV_DEBUG_TX_CLEAN     0x20000
#define DRV_DEBUG_CFG          0x40000
#define DRV_DEBUG_PHY          0x80000
#define DRV_DEBUG_DEBUG       0x100000
#define DRV_DEBUG_ALL       0xffffffff
#endif

/*
 * Defines for inputFlags in the ibmEmacEnd load string.  If none of the flags
 * below are set in the input string, the driver will use one transmit
 * channel, will use cached buffer/clusters (and manage the data cache
 * coherency), and will do transmits without copying (zero copy).  The flags
 * below can be used change the default behavior.
 */

#define EMAC_INPUT_TX_COPY       0x01          /* Do transmits with copy      */
#define EMAC_INPUT_UNCACHED_BUF  0x02          /* Use uncached buffers        */
#define EMAC_INPUT_TX_2_CHANNEL  0x04          /* Use both TX channels        */

/*
 * A common buffer descriptor structure is used for transmit and receive
 * operations.  Only the status/control bits have different meaning for TX
 * and RX. Bits 0:5 are used to control the RX and TX behavior of MAL on a
 * per-packet basis.  See malLib.h for the MAL buffer descriptor structure,
 * and the definitions of bits 0:5.
 *
 * Bits 6:15 are used to control the EMAC TX behavior, and to get status
 * about the TX and RX behavior of the EMAC on a per packet basis.
 */

/* EMAC Transmit Control */
#define EMAC_TX_CTRL_GFCS     0x0200           /* Generate FCS                */
#define EMAC_TX_CTRL_GP       0x0100           /* Generate padding            */
#define EMAC_TX_CTRL_ISA      0x0080           /* Insert source address       */
#define EMAC_TX_CTRL_RSA      0x0040           /* Replace source address      */
#define EMAC_TX_CTRL_IVT      0x0020           /* Insert VLAN tag             */
#define EMAC_TX_CTRL_RVT      0x0010           /* Replace VLAN tag            */

/* EMAC Transmit Status */
#define EMAC_TX_STAT_BFCS     0x0200           /* Bad FCS in packet           */
#define EMAC_TX_STAT_BPP      0x0100           /* Bad previous packet         */
#define EMAC_TX_STAT_LCS      0x0080           /* Loss of carrier sense       */
#define EMAC_TX_STAT_ED       0x0040           /* Excessive deferral          */
#define EMAC_TX_STAT_EC       0x0020           /* Excessive collisions        */
#define EMAC_TX_STAT_LC       0x0010           /* Late collision              */
#define EMAC_TX_STAT_MC       0x0008           /* Multiple collision          */
#define EMAC_TX_STAT_SC       0x0004           /* Single collision            */
#define EMAC_TX_STAT_UR       0x0002           /* Underrun                    */
#define EMAC_TX_STAT_SQE      0x0001           /* Signal quality error (SQE)  */
#define EMAC_TX_STAT          0x03FF           /* All TX STAT bits above      */

/* All the TX status bits that are considered errors */
#define EMAC_TX_ERRORS       (EMAC_TX_STAT_LCS  |  EMAC_TX_STAT_EC   |  \
                              EMAC_TX_STAT_LC   |  EMAC_TX_STAT_UR   |  \
                              EMAC_TX_STAT_SQE)

/* EMAC Receive Status */
#define EMAC_RX_STAT_OE       0x0200           /* Overrun error               */
#define EMAC_RX_STAT_PP       0x0100           /* Pause packet received       */
#define EMAC_RX_STAT_BP       0x0080           /* Bad packet                  */
#define EMAC_RX_STAT_RP       0x0040           /* Runt packet                 */
#define EMAC_RX_STAT_SE       0x0020           /* Short event                 */
#define EMAC_RX_STAT_AE       0x0010           /* Alignment error             */
#define EMAC_RX_STAT_BFCS     0x0008           /* Bad FCS                     */
#define EMAC_RX_STAT_PTL      0x0004           /* Packet too long             */
#define EMAC_RX_STAT_ORE      0x0002           /* Out of range error          */
#define EMAC_RX_STAT_IRE      0x0001           /* In range error              */
#define EMAC_RX_STAT          0x03FF           /* All RX STAT bits above      */

/* All the RX status bits that are considered errors */
#define EMAC_RX_ERRORS       (EMAC_RX_STAT_OE   |  EMAC_RX_STAT_BP   |  \
                              EMAC_RX_STAT_RP   |  EMAC_RX_STAT_SE   |  \
                              EMAC_RX_STAT_AE   |  EMAC_RX_STAT_BFCS |  \
                              EMAC_RX_STAT_PTL  |  EMAC_RX_STAT_ORE  |  \
                              EMAC_RX_STAT_IRE)

/*
 * Default descriptor initialization values.
 */

#define EMAC_TX_DESC_INIT       (EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP)

#define EMAC_RX_DESC_INIT       (MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR)


/* Definitions for localFlags bits in the EMAC_DRV_CTRL structure */

#define EMAC_HANDLE_RX_RUNNING    0x01        /* HandleRcvInt job running     */
#define EMAC_POLLING_MODE         0x02        /* Currently in polling mode    */
#define EMAC_TX_CLEAN_RUNNING     0x04        /* TX clean in progress         */
#define EMAC_TX_BLOCKED           0x08        /* Ran out of TX descriptors    */


/*
 * EMAC_BUF_SIZE is 1500 + 14 + 18 = 1532 which is 4 less than an even number
 * of 32 byte cache lines.  Add sizeof(long) cluster overhead and it is 1536.
 * The 18 bytes is padding.
 */

#define EMAC_BUF_SIZE       (ETHERMTU + SIZEOF_ETHERHEADER + 18)
#define EMAC_MIN_FBUF       100        /* Minsize of first buffer in chain */
#define EMAC_SPEED          10000000   /* 10Mbps                              */
#define EMAC_RXD_MIN        8          /* minimum # of RX descriptors/MAL chn */
#define EMAC_TXD_MIN        8          /* minimum # of TX descriptors/MAL chn */
#define EMAC_RXD_DFT        64         /* default # of RX descriptors/MAL chn */
#define EMAC_TXD_DFT        64         /* default # of TX descriptors/MAL chn */
#define EMAC_RXD_MAX        MAL_MAX_DESC   /* max # of RX descriptors/MAL chn */
#define EMAC_TXD_MAX        MAL_MAX_DESC   /* max # of TX descriptors/MAL chn */

#define EMAC_RXD_LOAN_X	    4		/* multiply no. of RX desc. to allow */
					/* for buffer loaning		     */

#define EMAC_DEV_NAME       "emac"      /* Name of this device - max 4 char  */
#define EMAC_DEV_DESC       "IBM EMAC End Driver"     /* Description          */

/*
 * Basic unit, maximum, minimum, and default memory sizes.
 * The sizeof(long) in EMAC_BSC_MEM_SIZE is for cluster overhead.
 */
#define EMAC_BSC_MEM_SIZE    (EMAC_BUF_SIZE + sizeof(long))
#define EMAC_MAX_MEM_SIZE    ((EMAC_RXD_MAX * EMAC_RXD_LOAN_X + EMAC_TXD_MAX) \
			      * EMAC_BSC_MEM_SIZE)
#define EMAC_MIN_MEM_SIZE    ((EMAC_RXD_MIN * EMAC_RXD_LOAN_X + EMAC_TXD_MIN) \
			      * EMAC_BSC_MEM_SIZE)
#define EMAC_DFT_MEM_SIZE    ((EMAC_RXD_DFT * EMAC_RXD_LOAN_X + EMAC_TXD_DFT) \
			      * EMAC_BSC_MEM_SIZE)


/* Multiple Individual and Group Address Filter definitions */

#define EMAC_FILTER_CRC_POLY  0x04C11DB6
#define EMAC_ADDR_BYTES       6
#define EMAC_ADDR_BITS        8


/* Structure to keep track of resources to be freed by ibmEmacSendCleanup */

typedef struct
    {
    UINT     typeFree;                   /* Cluster or Mblk                  */
    UCHAR  * pFree;                      /* Cluster address, Mblk, etc.      */
    } EMAC_FREE;