config.h

WINDRIVER SBC405 BSP

/* config.h - Wind River SBC405GP configuration header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01l,21jan03,pch  Update BSP_REV for SPR 80226 fix.
01k,12jul02,pch  SPR 78057:  enable coexistence of emac and fei
01j,26jun02,pch  SPR 73650 & 76704: clean up refs to processor revisions
01i,17apr02,jtp  SPR#73673 turn off I-MMU to reduce TLB Entry register
                 contention
01h,17feb02,g_h  Add the NO_NETWORK option to BOOT_DEVICE type
01g,29jan02,g_h  Add #undef NV_RAM_SIZE before re-defining it again.
01f,18jan02,g_h  Change ROM_SIZE to 2MB - reserved space for reset vector.
01e,18jan02,g_h  Add MAC_ADRS_LEN macro
01d,11jan02,pch  Move WRONG_CPU_MSG defn from ppc405GP.h to config.h
01c,22nov01,g_h  Cleaning for T2.2
01b,17sep01,g_h  update to reflect the changes done in T2CP4
01a,22apr01,g_h  created from Walnut config.h version 01l.
*/

/*
This file contains the configuration parameters for the
Wind River SBC 405GP CPU evaluation board.
*/

#ifndef __INCconfigh
#define __INCconfigh

#ifdef __cplusplus
extern "C" {
#endif

/* BSP version/revision identification, before configAll.h */
#define BSP_VER_1_1     0
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"           /* A Tornado 2.0 BSP    */
#define BSP_REV         "/7"            /* 0 for first revision */

#include "configAll.h"

/* CPU configuration */

/* Message displayed for unrecognized processor */
#define WRONG_CPU_MSG "Unsupported processor version ";

/* Memory configuration */

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
 * are defined in config.h and Makefile.
 * All definitions for these constants must be identical.
 *
 * Boot ROM address space.
 */

#define ROM_BASE_ADRS        0xFFE00000	             /* base address of ROM  */
#define ROM_TEXT_ADRS        (ROM_BASE_ADRS + NV_RAM_SIZE) /* with PC & SP   */
#define ROM_WARM_ADRS        (ROM_TEXT_ADRS+0x0004)  /* warm reboot entry    */
#define ROM_SIZE             0x001FFE00		     /* 2MB                  */
#define RAM_LOW_ADRS         0x00010000		     /* RAM addr for vxWorks */
#define RAM_HIGH_ADRS        0x01C00000		     /* RAM addr for bootrom */
#define LOCAL_MEM_SIZE       0x04000000              /* 64 memory default    */
#define LOCAL_MEM_LOCAL_ADRS 0x00000000              /* Fixed at zero        */
#define USER_RESERVED_MEM    0x02000000		     /* see sysMemTop()      */

/* Serial port configuration */

#define  INCLUDE_SIO

/*
 * The clock used to drive the UARTs on the 405GP can be derived from
 * one of two different sources.  The 11.0592 MHz external oscillator on SBC405GP
 * can be used, or the CPU clock can be used with an additional internal UART
 * divisor (see the CPC0_CR0 register).  If you do not want to use the external
 * UART clock oscillator, undef UART_CLOCK_EXTERNAL
 * NOTE: Revs B, C and D of the 405GP have an errata which prevents the
 * internal divisor to work at different rates. So if you want to use a 
 * different console BAUD rate, it is recommended that you use the external
 * clock.
 */

#define  UART_CLOCK_EXTERNAL      /* define to use external 11.0592 MHz clock */

/* Timer configuration */

#define  INCLUDE_AUX_CLK
#define  INCLUDE_TIMESTAMP

/*
 * 405 timers (PIT, FIT, WDT) can be driven from an external clock source,
 * or at the same frequency as the CPU.
 */

#undef TIMER_CLOCK_EXTERNAL

/* EMAC MAC address configuration */

/*
 * The Ethernet hardware address that is used with EMAC is
 *
 *       0x00A01Ennnnnn
 *
 * where the first three bytes are defined below, and last three bytes are
 * stored in the NVRAM and can be modified by using the function
 * sysLanIbmEmacEnetAddrSet()
 */
/*                                    ___ Alignment pad */
/*                                   |                  */
/*                                  \|/                 */
#define ENET_DEFAULT         0x00A01E00 /* WRS fixed MAC addr */

#define MAC_ADRS_LEN	     6

/* NvRAM configuration */             

#define NV_RAM_ADRS          ROM_BASE_ADRS
#define NV_RAM_SIZE          0x200
#undef  NV_BOOT_OFFSET
#define NV_BOOT_OFFSET	     0
#define NV_ENET_OFFSET	     0x1F0 /* Offset of Ethernet HW adrs from the boot offset */

/* Cache configuration  */

#define INCLUDE_CACHE_SUPPORT
#define USER_I_CACHE_ENABLE  
#define USER_D_CACHE_ENABLE  
#undef	USER_D_CACHE_MODE
#define USER_D_CACHE_MODE    CACHE_COPYBACK /* select COPYBACK or WRITETHROUGH */

/*
 * MMU configuration
 *
 * Note: leaving I-MMU disabled reduces contention for the 64 available
 * UTLB Entries. This typically improves application performance.
 */

#define INCLUDE_MMU_BASIC
#undef  INCLUDE_MMU_FULL
#undef USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE

/*
 * On the 405 CPU we cannot enable the MMU unless the caches are initialized
 * (unless ofcourse we mark the entire address space as un-cacheable). There
 * is no separate way of disabling the caches when the MMU is enabled, other
 * than on a page-by-page basis. Hence it is recommended that caches always
 * be used whenever the MMU is used.
 */
#ifdef INCLUDE_MMU_BASIC
    #ifndef INCLUDE_CACHE_SUPPORT
    #error "You need to include Cache support for MMU support."
    #endif
#endif

/* PCI configuration */

#define INCLUDE_PCI

#ifdef  INCLUDE_PCI
#define INCLUDE_SHOW_ROUTINES 
#define INCLUDE_PCI_AUTOCONF
#define PCI_LAT_TIMER        255 /* PCI Latency Timer value */

#ifndef PCI_CFG_TYPE
#   ifdef INCLUDE_PCI_AUTOCONF
#      define PCI_CFG_TYPE PCI_CFG_AUTO
#   else
#      define PCI_CFG_TYPE PCI_CFG_FORCE
#   endif /* INCLUDE_PCI_AUTOCONF */
#endif /* PCI_CFG_TYPE */

#endif /* INCLUDE_PCI */

/* Software floating point support */

#undef INCLUDE_SW_FP

/* Wind River FPGA card support */

#undef  INCLUDE_WR_FPGA_CARD

#ifdef  INCLUDE_WR_FPGA_CARD
#define WR_FPGA_CARD_ON_LOCAL_BUS
#endif  /*INCLUDE_WR_FPGA_CARD */

/* Network driver configuration */

#define	INCLUDE_NETWORK
#define INCLUDE_NET_INIT
#undef  INCLUDE_EI
#undef  INCLUDE_LN
#undef  INCLUDE_BP
#undef	INCLUDE_EX
#undef	INCLUDE_ENP
#undef	INCLUDE_SM_NET
#undef  INCLUDE_SM_SEQ_ADDR

/* Only if using network */

#ifdef	INCLUDE_NETWORK

/* Enhanced Network Driver (END) support */

#define	INCLUDE_END		/* Enhanced Network Driver (see configNet.h) */
#undef  INCLUDE_BSD		/* BSD 4.4 drivers (not supported) */

/* Network Driver Types */

#define NO_NETWORK           0
#define EMAC_END	     1  /* build in the EMAC driver */
#define FEI_END		     2  /* build in the FEI driver */

#define BOOT_DEVICE  EMAC_END /* Choose your Boot Device: EMAC_END or FEI_END */

#undef	BOTH_NET	/* build in both drivers, BOOT_DEVICE chooses primary */

#if defined(BOTH_NET) || (BOOT_DEVICE == EMAC_END)
  /*
   * Optimized data cache flush and invalidate functions for ibmEmacEnd
   */

  #define EMAC_CACHE_FLUSH(address, len) \
          cacheFlush405 (_DATA_CACHE, (address), (len))

  #define EMAC_CACHE_INVALIDATE(address, len) \
          cacheInvalidate405 (_DATA_CACHE, (address), (len))
#endif	/* BOTH_NET || BOOT_DEVICE == EMAC_END */

#else	/* INCLUDE_NETWORK */
  #define BOOT_DEVICE NO_NETWORK
  #undef  BOTH_NET
#endif	/* INCLUDE_NETWORK */

/* Boot device */

#if (BOOT_DEVICE == EMAC_END)
  #define BOOT_DEV_NAME      "emac"
  #define INCLUDE_EMAC_NETWORK	 /* include 405GP native EMAC network support */
  #define ETHERNET_ADR_SET    /* (used in bootConfig.c to enable 'N' command) */
  #undef  WDB_COMM_TYPE
  #define WDB_COMM_TYPE      WDB_COMM_END	
  #ifdef BOTH_NET
    #define INCLUDE_FEI82557END		/* also include FEI driver */
  #endif /* BOTH_NET */

#elif (BOOT_DEVICE == FEI_END)
  #define BOOT_DEV_NAME      "fei"
  #define INCLUDE_FEI82557END		/* include FEI driver */
  #undef  WDB_COMM_TYPE
  #define WDB_COMM_TYPE      WDB_COMM_END
  #ifdef BOTH_NET
    #define INCLUDE_EMAC_NETWORK	/* also include EMAC */
  #endif /* BOTH_NET */
#elif (BOOT_DEVICE == NO_NETWORK)
  #define BOOT_DEV_NAME      "none"
  #undef  INCLUDE_FEI82557END
  #undef  INCLUDE_EMAC_NETWORK
#else	/* BOOT_DEVICE */
 #define BOOT_DEV_NAME "none"
#endif	/* BOOT_DEVICE */

/* Debuging configuration */

/* 			
 * If the FORCE_DEFAULT_BOOT_LINE is defined then the DEFAULT_BOOT_LINE
 * parameters are always used regardless of NVRAM values specified at
 * bootrom time. See target.nr for details. This is usually used to debug
 * WR downloaded images with out a bootrom present.
 */
#undef  FORCE_DEFAULT_BOOT_LINE

#ifdef  INCLUDE_WDB_COMM_VTMD
#define FORCE_DEFAULT_BOOT_LINE /* When using TMD this macro should be undefined */
#endif  /* INCLUDE_WDB_COMM_VTMD */

/* visionWARE configuration */

#define INCLUDE_VWARE_LAUNCH

/* Stuff to be excluded if FORCE_DEFAULT_BOOT_LINE defined */

#ifdef  FORCE_DEFAULT_BOOT_LINE
#undef  INCLUDE_VWARE_LAUNCH
#undef  ETHERNET_ADR_SET
#undef  NV_RAM_SIZE
#define NV_RAM_SIZE          NONE
#endif  /* FORCE_DEFAULT_BOOT_LINE */

/* Boot line configuration */

#if defined(BOOT_DEV_NAME)
#define DEFAULT_BOOT_LINE    BOOT_DEV_NAME \
                             "(0,0)sbc405gp:vxWorks " \
                             "e=24.42.124.92 " \
                             "h=24.42.124.94 " \
                             "g=0.0.0.0 "  \
                             "u=anonymous pw=user "     \
                             "f=0x00 tn=sbc405gp"

#ifdef INCLUDE_VWARE_LAUNCH
#define VWARE_BOOT_LINE	     BOOT_DEV_NAME \
                             "(0,0)sbc405gp:vxworks " \
                             "%s " \
                             "%s " \
                             "%s " \
                             "u=anonymous pw=user " \
                             "f=0x000 tn=sbc405gp" 
#endif /* INCLUDE_VWARE_LAUNCH */
#endif /* BOOT_DEV_NAME */

/*
 * User application initialization
 *
 * USER_APPL_INIT must be a valid C statement or block.  It is
 * included in the usrRoot() routine only if INCLUDE_USER_APPL is
 * defined.  The code for USER_APPL_INIT is only an example.  The
 * user is expected to change it as needed.  The use of taskSpawn
 * is recommended over direct execution of the user routine.
 */

#undef	INCLUDE_USER_APPL
#define	USER_APPL_INIT \
	{ \
	IMPORT int myAppInit(); \
	taskSpawn ("myApp", 30, 0, 5120, \
		   myAppInit, 0x1, 0x2, 0x3, 0,0,0,0,0,0,0); \
	}

/* Include hardware header file */

#include "wrSbc405gp.h"        /* board header file          */
#include "ppc405GP.h"          /* chip header file           */

#if defined(EMAC_CACHE_FLUSH) || defined(EMAC_CACHE_INVALIDATE)
#include "405cache.h"
#endif /* defined(EMAC_CACHE_FLUSH) || defined(EMAC_CACHE_INVALIDATE) */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif	/* __INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif