target.nr

WINDRIVER SBC405 BSP

device and the IBM EMAC as an Ethernet.

.SS "Default Memory Map"
.CS
        Memory Map from CPU point of view

Start               Size         Access to
---------------------------------------------------------------------
0x0                 64MB (min)   SDRAM SODIMM
0xFF000000	    16MB         On Board FLASH
0xEF600000	     4KB         UART + OPB + IIC (Registers)
0x80000000          ----         PCI non-prefetchable memory
0xE8800000         100MB         PCI 32 bit IO space
0xE8000000           4KB         PCI 16 bit IO space
.CE

.SS "Memory Maps"

This BSP supports MMU on the PPC405GP processor. Memory is mapped using a
fixed page size of 4K.

The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table 
Entry (PTE) array used by the MMU to translate addresses with single page 
(4k) granularity. Address translations for local RAM, and local PROM/FLASH
are set here. PTEs are held in a 2-level page table. There is one Level 1 
page table and several Level 2 page tables. The size of the Level 1 table 
is 4K and the size of each Level 2 page table is 8K. Each Level 2 table 
can map upto 4MB of contiguous memory space.

.SS "Calculating size of page table required"

For the following memory map we can calculate the page table size 
required as follows:

.TS
expand;
l l l l .
Memory Area	Address Range Mapped	Size	Number of Level 2 pages
-
Local Memory    0 - Ram size            32MB 8
PCI Memory      0x80000000-0x83FFFFFF   64MB 16
PCI IO Regn 1   0xE8000000-0xE800FFFF   64K  1
PCI IO Regn 2   0xE8800000-0xE88FFFFF   1MB  1
PCI CFG         0xEEC00000-0xEEC00FFF   4K   1
PCI IACK        0xEED00000-0xEED00FFF   4K   0 *
PP Bridge       0xEF400000-0xEF400FFF   4K   1
UART IO Space   0xEF600000-0xEF600FFF   4K   0 *
Flash           0xFF000000-0xFFFFFFFF   16MB 4
.TE

	* included in previous L2 page 

	Total # of L2 pages = 32
	Total Memory Required for page table = 32 * 8 + 4 = 260 K.

By default, to increase performance the instruction MMU (IMMU) is turned
off. In this case, instruction cacheability is controlled by ICCR (which
by default is set to cache all RAM). The IMMU can be re-enabled by defining 
USER_I_MMU_ENABLE in config.h.

.SS "Shared Memory"
NA

.SS " NVRAM Support" 
This BSP emulate NvRam via a the On Board FLASH device. There are a few user 
parameters associated with this device. The parameters are located in
the "config.h" file and are:
.CS  
    #define ETHERNET_ADR_SET /* (used in bootConfig.c to enable 'N' command) */
.CE

The ETHERNET_ADR_SET is a macro that indicates the MAC address is stored in NVRAM 
and alterable via the 'N' bootrom command.


.SS "Network Configuration"
The Enhanced Network Driver (END) used with the integrated EMAC Ethernet
core is "ibmEmacEnd" or the Intel 82559 (FEI) PCI Ehternet controller. 
The EMAC & FEI works at either 10Mbps or 100Mbps. EMAC gets the results 
of the PHY's auto-negotiation process over the MII interface.

Since MAL is a Processor Local Bus (PLB) master, its accesses to system
memory are unknown to the processor's L1 cache because there is no hardware
enforced cache coherency in the 405GP.  The ibmEmacEnd driver maintains
coherency for both buffer descriptors and buffers.

The following are not supported in the current driver:

    - TX channel 1
     - wake-on-LAN

The Ethernet hardware address is configurable at run-time.
The first three bytes of the address are always assumed to be 0x00A01E
(Wind River) and the last three bytes are configurable and stored in NVRAM at
address 0xFFE001F0.

If desired, an Intel 82559 PCI Ethernet card can be plugged into the SBC405GP
board.  This controller uses the fei82557End driver provided with VxWorks.

.SS "Changing the Ethernet Address for the EMAC interface"
The SBC405GP boards do not have a unique Ethernet hardware address 
assigned to each board. A unique address is absolutely necessary if the
user wishes to connect the board to a network. Thus, the user must 
provide a suitable 6 byte Ethernet address for each board used
on a network. The first 3 byte are Wind River specific and they
specified in "config.h" the last 3 byte are use specific and thet
specified in the NvRam and can be changes by using the 'N' option in
the bootrom prompt or from the shell.

1. Changing the first three bytes:

    The first three bytes (0x00, 0xa0, 0x1e) are a Wind River specific prefix
    that should be kept as-is. If for some reason you need to change them, in
    "config.h" change the following macros:
.CS
    #define ENET_DEFAULT 0x00A01E00
.CE

    If these bytes need changing (they often will not), a new boot ROM must be 
    burned, and a new image must be built. 

2. Changing the last three byts:

    The last three bytes of the Ethernet Address can be specified at the 
    bootrom prompt (N command) or at the shell prompt. The last three bytes of 
    the Ethernet address are stored in the on board NVRAM.
   
    2.1. Changing the last three bytes from the bootrom prompt: 
      
         This option will able you to change the last three bytes from the 
         bootrom prompt. To use this option, open the console window (for 
         example: "Hyper terminal") and when the bootrom banner appear and the 
         countdown start, press any key, when you get the "[VxWorks Boot]" 
         prompt, press 'N' and follow the instructions.

    2.2. Changing the last three bytes from the shell prompt:

         This option will able you to change the last three bytes from the 
         shell prompt. To use this option follow those step:

         1. Boot VxWorks.

         2. Execute the following command from the shell:

         If the Ethernet address last three bytes are:  11 22 33
.CS
         sysLanIbmEmacEnetAddrSet 0x00, 0x00, 0x00, 0x11, 0x22, 0x33
.CE

.SS "Switching between the EMAC to FEI"
The BSP "as supplied" is configured for the EMAC driver, but it can also
support the FEI driver that is used for Intel 82557, 82558, and 82559 devices.
To configure the BSP for the FEI driver instead of the EMAC:

    1. In "config.h" change the following line:

       FROM:
.CS
       #define BOOT_DEVICE          EMAC_END
.CE
       TO:
.CS
       #define BOOT_DEVICE          FEI_END
.CE

    2. Now rebuild the bootrom and create a new VxWorks image project and build 
       it.

    ** Don't forget to change the device name to "fei" in the "boot device" 
       line in the bootrom.

.SS "BOOT FLASH"
The BSP configures to use the 16MByte On Board Flash. This is the only Flash on 
the board.

.SS "Serial Configuration"
The default configuration of the serial ports are 9600bps, 8 data bits, 
no parity, 1 stop bit.

.SS "Serial Connections"
This VxWorks SBC405GP board uses a simple 3 wire connection and standard 
phone jacks where pin 1 = RIN, pin 2 = TOUT, pin 3 = NC, and pin 4 = GND.

.SS "SCSI Configuration"
There is no SCSI interface on this board.

.SS "VME Access"
NA

.SS "PCI Access"
The board contain one 32-bit address, 32-bit data; complies with PCI Local Bus
Specification, Revision 2.1 the PPC405GP is the PCI bridge. The current
version of the BSP is supporting the pciConfigLib & pciAutoConfigLib.

.SS "Wind River FPGA card (Proteus)"
The wrSbc405gp BSP support the Wind River FPGA card. This card is an optional
product sold separately. The support is done by supplying the user a load routine
that load the FPGA. The Wind River FPGA card can be connected to the 405 External 
Bus or to the PCI bus by connecting it to the PMC slot, currently only the 
405 External Bus option is supported. To add the support for the card the user
need to plug the card to the SBC405GP External Bus connectors those connectors
are marked on the board as "CUSTOM Mezzanine SLOT" and to change the following
line in "config.h"

From:
.CS
     /* Wind River FPGA card support */

     #undef  INCLUDE_WR_FPGA_CARD
.CE

To:

.CS
     /* Wind River FPGA card support */

     #define  INCLUDE_WR_FPGA_CARD
.CE

And re-build the bootrom and the vxWorks image. This will initialize the 
necessary CS and map the card in the MMU table. One of the simple option to load
the FPGA is by using the Target Server File System (TSFS), to do this make sure
that "INCLUDE_WDB_TSFS" is defined in your vxWorks image, this is for the WDB
target server file system. Done forget to enable to Read/Write permission the
target server file system in the target server configuration.

Here is example how to load the FPGA from the WindSH:

.CS
     -> sysProteusLoad ("/tgtsvr/filename.bit")
.CE 

.SS "Delivered Objects"
The following images are delivered with the wrSbc405gp BSP:

.IP
bootrom
.IP
bootrom.hex
.IP
vxWorks
.IP
vxWorks.st
.LP

.SS "Make Targets"
Only bootrom_uncmp, bootrom & vxWorks have been tested.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information that the user needs
to know about the BSP.

.SS "Debugging VxWorks application with visionPROBE II/visionICE II"
To use visionPROBE II/visionICE II with BSP code or VxWorks application code,
the following "CF" option need to be set:

.CS
    CF TRPEXP NO
.CE

To do this, go to the visionCLICK/visionXD terminal window and type the
command "CF TRPEXP NO" and press enter, then type "IN" and press enter.

.SS "Location of the boot code"
The PPC405GP reset vector is located at 0xFFFFFFFC. That enable us to locate 
the boot code anywhere in the Flash. The default location of the boot code is
in the begining of the Flash at 0xFFE00200 (The first 0x200 is used for NvRam).
if you desire to move it you need to change the following:

1. Changing the macro "ROM_BASE_ADRS" in the "config" reflect the new address.

2. Changing the macro "ROM_TEXT_ADRS" in the "Makefile" reflect the new
   ROM_BASE_ADRS + NV_RAM_SIZE for example: 

   If the new ROM_BASE_ADRS = 0xFFF80000 & NV_RAM_SIZE = 0x200 then the new
   ROM_TEXT_ADRS should be equl to 0xFFF80200

3. Programing a new branch absolute command at address 0xFFFFFFFC, the original
   branch command that comes with the BSP is "ba FFE00000"

.SS "Processor errata"
There are errata in the 405GP processor which affect the operation of
this Board Support Package.  You should familiarize yourself with them.
A current 405GP errata list is available from the PowerPC Technical
support group ([e-mail]).

.SS "Known Problems"
N/A

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration," 
.pG "Architecture Appendix"

.SH "BIBLIOGRAPHY"
Please refer to the following documents for further information on the
SBC405GP board.

.iB "PowerPC 405GP Embedded Processor User's Manual"
.iB "SBC405GP User's Manual".