ppc405gp.h

WINDRIVER SBC405 BSP

/* ppc405GP.h - IBM PowerPC 405GP Chip header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
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   license.

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   licensors will be responsible for any consequences resulting from the use
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   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01k,20aug02,pch  405GP / 405GPr interoperability
01j,18jun02,mcg  add support for 405GPr new registers and bits
01i,12jun02,pch  SPR 74987: C++
01h,09jan02,pch  Change MAL, ENET, and EBC references to MAL0, ENET0, EBC0 for
                 consistency with ebony
01g,19nov01,pch  cleanup
01f,06dec00,s_m  added Rev E PVR
01e,26may00,mcg  moved DMA register information to its own header file
01d,15may00,mcg  register name updates to match 405GP User Manual
01c,18apr00,mcg  fix PCI_IO_REGION_X definitions
01b,15jan00,mcg  move MAL, UIC, SDRAM controller info to their own .h files
01a,09sep99,mcg  created
*/

/*
This file contains DCR (Device Control Register) addresses and other chip
specific information for the IBM PowerPC 405GP outside of the 405 processor
core (see ppc405.h for 405 processor core information).
*/

#ifndef INCppc405GPh
#define INCppc405GPh

#ifdef __cplusplus
    extern "C" {
#endif

/*
 * The 405GP chip uses the 405B3 processor core which has a 16KB I-cache and a
 * 8KB D-cache.  All 405 processor cores have 32 byte cache lines, and are
 * 2-way set associative.
 */

#define _ICACHE_LINE_NUM_405GP 256                     /* 256 * 32 * 2 = 16KB */
#define _DCACHE_LINE_NUM_405GP 128                     /* 128 * 32 * 2 =  8KB */

/*
 * The 405GPr chip uses the 405D4 processor core which has a 16KB I-cache and a
 * 16KB D-cache.  All 405 processor cores have 32 byte cache lines, and are
 * 2-way set associative.
 */

#define _ICACHE_LINE_NUM_405GPR 256                    /* 256 * 32 * 2 = 16KB */
#define _DCACHE_LINE_NUM_405GPR 256                    /* 256 * 32 * 2 = 16KB */


/*
 * Processor Version Register (PVR) values for 405GP and 405GPr
 */

/*#define PVR_405GP_RA  0x40110000    405GP Revision A (not supported) */
#define PVR_405GP_RB    0x40110040        /* 405GP Revision B                 */
#define PVR_405GP_RC    0x40110082        /* 405GP Revision C                 */
#define PVR_405GP_RD    0x401100C4        /* 405GP Revision D                 */
#define PVR_405GP_RE    0x40110145        /* 405GP Revision E                 */
#define PVR_405GPR_RB   0x50910951        /* 405GPr Revision B (1.1)          */

#define PVR_405GP_HI    0x4011		/* generic 405GP recognition */

/*
 * Reduce the number of MAL channel DCR access functions because a MAL with
 * only 8 channels is used in the 405GP.
 */

#define MAL_CHANNELS_8

/*
 * Valid Memory Access Layer (MAL) channels.  On the 405GP, EMAC is the only
 * communications core that uses MAL.  It has 2 TX channels, and 1 TX channel.
 */

#define MAL_CHN_TX_CPUCORE	0xC0000000	/* TX channels 0 and 1       */
#define MAL_CHN_RX_CPUCORE	0x80000000	/* RX channel  0             */

/*
 * MAL channels numbers the EMAC Ethernet controller is connected to on 405GP.
 * This information is put into the EMAC driver END load string.
 */

#define EMAC0_TX_CHN_0_CPUCORE	0
#define EMAC0_TX_CHN_1_CPUCORE	1
#define EMAC0_RX_CHN_0_CPUCORE	0

/*
 * Base DCR address values for all perhipheral cores in the 405GP
 */

#define SDRAM_DCR_BASE        0x010       /* SDRAM Controller                 */
#define EBC0_DCR_BASE         0x012       /* External Bus Controller          */
#define UIC_DCR_BASE          0x0C0       /* Universal Interrupt Controller   */
#define DMA_DCR_BASE          0x100       /* DMA Controller                   */
#define CLKPWRCH_DCR_BASE     0x0B0       /* Clock/Power/Chip Control         */
#define MAL0_DCR_BASE         0x180       /* Memory Access Layer Core         */
#define DECOMP_DCR_BASE       0x014       /* Code Decompression Core          */
#define OCM_DCR_BASE          0x018       /* On-chip Memory Controller        */

/*
 * Static interrupt vectors/levels.  These also correspond to bit numbers in
 * many of the registers of the Universal Interrupt Controller.
 */
#define INT_VEC_UART0             0
#define INT_VEC_UART1             1
#define INT_VEC_IIC               2
#define INT_VEC_EXT_MASTER        3
#define INT_VEC_PCI               4
#define INT_VEC_DMA_CH0           5
#define INT_VEC_DMA_CH1           6
#define INT_VEC_DMA_CH2           7
#define INT_VEC_DMA_CH3           8
#define INT_VEC_ENET_WAKEUP       9
#define INT_VEC_MAL_SERR          10
#define INT_VEC_MAL_TXEOB         11
#define INT_VEC_MAL_RXEOB         12
#define INT_VEC_MAL_TXDE          13
#define INT_VEC_MAL_RXDE          14
#define INT_VEC_ENET_0            15
#define INT_VEC_PCI_SERR          16
#define INT_VEC_ECC_ERROR         17
#define INT_VEC_PCI_POWER         18
#define INT_VEC_EXT_IRQ_7         19                /* 405GPr only */
#define INT_VEC_EXT_IRQ_8         20                /* 405GPr only */
#define INT_VEC_EXT_IRQ_9         21                /* 405GPr only */
#define INT_VEC_EXT_IRQ_10        22                /* 405GPr only */
#define INT_VEC_EXT_IRQ_11        23                /* 405GPr only */
#define INT_VEC_EXT_IRQ_12        24                /* 405GPr only */
#define INT_VEC_EXT_IRQ_0         25
#define INT_VEC_EXT_IRQ_1         26
#define INT_VEC_EXT_IRQ_2         27
#define INT_VEC_EXT_IRQ_3         28
#define INT_VEC_EXT_IRQ_4         29
#define INT_VEC_EXT_IRQ_5         30
#define INT_VEC_EXT_IRQ_6         31

#define INT_LVL_UART0             0
#define INT_LVL_UART1             1
#define INT_LVL_IIC               2
#define INT_LVL_EXT_MASTER        3
#define INT_LVL_PCI               4
#define INT_LVL_DMA_CH0           5
#define INT_LVL_DMA_CH1           6
#define INT_LVL_DMA_CH2           7
#define INT_LVL_DMA_CH3           8
#define INT_LVL_ENET_WAKEUP       9
#define INT_LVL_MAL_SERR          10
#define INT_LVL_MAL_TXEOB         11
#define INT_LVL_MAL_RXEOB         12
#define INT_LVL_MAL_TXDE          13
#define INT_LVL_MAL_RXDE          14
#define INT_LVL_ENET_0            15
#define INT_LVL_PCI_SERR          16
#define INT_LVL_ECC_ERROR         17
#define INT_LVL_PCI_POWER         18
#define INT_LVL_EXT_IRQ_7         19                /* 405GPr only */
#define INT_LVL_EXT_IRQ_8         20                /* 405GPr only */
#define INT_LVL_EXT_IRQ_9         21                /* 405GPr only */
#define INT_LVL_EXT_IRQ_10        22                /* 405GPr only */
#define INT_LVL_EXT_IRQ_11        23                /* 405GPr only */
#define INT_LVL_EXT_IRQ_12        24                /* 405GPr only */
#define INT_LVL_EXT_IRQ_0         25
#define INT_LVL_EXT_IRQ_1         26
#define INT_LVL_EXT_IRQ_2         27
#define INT_LVL_EXT_IRQ_3         28
#define INT_LVL_EXT_IRQ_4         29
#define INT_LVL_EXT_IRQ_5         30
#define INT_LVL_EXT_IRQ_6         31

/*
 * Clock, power management, chip control and strapping register defintions.
 * Each is a separate DCR register.
 */
#define CPC0_PLLMR  (CLKPWRCH_DCR_BASE+0x0)  /* PLL Mode Register             */
#define CPC0_CR0    (CLKPWRCH_DCR_BASE+0x1)  /* Chip control 0 Register       */
#define CPC0_CR1    (CLKPWRCH_DCR_BASE+0x2)  /* Chip control 1 Register       */
#define CPC0_PSR    (CLKPWRCH_DCR_BASE+0x4)  /* Pin Strapping Register        */
#define CPC0_SR     (CLKPWRCH_DCR_BASE+0x8)  /* clock/power management status */
#define CPC0_ER     (CLKPWRCH_DCR_BASE+0x9)  /* clock/power management enable */
#define CPC0_FR     (CLKPWRCH_DCR_BASE+0xa)  /* clock/power management force  */
#define CPC0_ECID0       0xA8                /* 405GPr only chip id upper     */
#define CPC0_ECID1       0xA9                /* 405GPr only chip id lower     */
#define CPC0_ECR         0xAA                /* 405GPr only edge conditioner  */
#define CPC0_EIRR   (CLKPWRCH_DCR_BASE+0x6)  /* 405GPr ext interrupt routing  */

/* Bit definitions */
#define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
#define PLLMR_FWD_DIV_BIT_SHIFT     29
#define PLLMR_FWD_DIV_BYPASS    0xE0000000
#define PLLMR_FWD_DIV_3         0xA0000000
#define PLLMR_FWD_DIV_4         0x80000000
#define PLLMR_FWD_DIV_6         0x40000000

#define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
#define PLLMR_FB_DIV_BIT_SHIFT      25
#define PLLMR_FB_DIV_1          0x02000000
#define PLLMR_FB_DIV_2          0x04000000
#define PLLMR_FB_DIV_3          0x06000000
#define PLLMR_FB_DIV_4          0x08000000

#define PLLMR_TUNING_MASK       0x01F80000

#define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
#define PLLMR_CPU_TO_PLB_BIT_SHIFT  17
#define PLLMR_CPU_PLB_DIV_1     0x00000000
#define PLLMR_CPU_PLB_DIV_2     0x00020000
#define PLLMR_CPU_PLB_DIV_3     0x00040000
#define PLLMR_CPU_PLB_DIV_4     0x00060000

#define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
#define PLLMR_OPB_TO_PLB_BIT_SHIFT  15
#define PLLMR_OPB_PLB_DIV_1     0x00000000
#define PLLMR_OPB_PLB_DIV_2     0x00008000
#define PLLMR_OPB_PLB_DIV_3     0x00010000
#define PLLMR_OPB_PLB_DIV_4     0x00018000

#define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
#define PLLMR_PCI_TO_PLB_BIT_SHIFT  13
#define PLLMR_PCI_PLB_DIV_1     0x00000000
#define PLLMR_PCI_PLB_DIV_2     0x00002000
#define PLLMR_PCI_PLB_DIV_3     0x00004000
#define PLLMR_PCI_PLB_DIV_4     0x00006000

#define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
#define PLLMR_EXB_TO_PLB_BIT_SHIFT  11
#define PLLMR_EXB_PLB_DIV_2     0x00000000
#define PLLMR_EXB_PLB_DIV_3     0x00000800
#define PLLMR_EXB_PLB_DIV_4     0x00001000
#define PLLMR_EXB_PLB_DIV_5     0x00001800

#define PLLMR_TUNING_MASK_UPPER 0x00000780     /* 405GPr only               */

#define PLLMR_BYPASS_MODE       0x00000040     /* 405GPr only               */

#define PLLMR_FWD_DIVB_MASK     0x00000007     /* Forward Divisor           */
#define PLLMR_FWD_DIVB_BIT_SHIFT     0
#define PLLMR_FWD_DIVB_8        0x00000000     /* 405GPr only               */
#define PLLMR_FWD_DIVB_7        0x00000001
#define PLLMR_FWD_DIVB_6        0x00000002
#define PLLMR_FWD_DIVB_5        0x00000003
#define PLLMR_FWD_DIVB_4        0x00000004
#define PLLMR_FWD_DIVB_3        0x00000005
#define PLLMR_FWD_DIVB_2        0x00000006
#define PLLMR_FWD_DIVB_1        0x00000007

/*
 * PLL Voltage Controlled Oscillator (VCO) definitions
 * Maximum and minimum values (in MHz) for correct PLL operation.
 *    405GP    400 <= VCO <= 800
 *    405GPr   400 <= VCO <= 1333
 */
#define VCO_MIN_GP	400
#define VCO_MAX_GP	800
#define VCO_MIN_GPR	400
#define VCO_MAX_GPR	1333

/* Chip Control Register 0 bits */
#define CR0_PLL_MODE_REG_EN     0x80000000
#define CR0_GPIO_10_EN          0x04000000
#define CR0_GPIO_11_EN          0x02000000
#define CR0_GPIO_12_EN          0x01000000
#define CR0_GPIO_13_EN          0x00800000
#define CR0_GPIO_14_EN          0x00400000
#define CR0_GPIO_15_EN          0x00200000
#define CR0_GPIO_16_EN          0x00100000
#define CR0_GPIO_17_EN          0x00080000
#define CR0_GPIO_18_EN          0x00040000
#define CR0_GPIO_19_EN          0x00020000
#define CR0_GPIO_20_EN          0x00010000
#define CR0_GPIO_21_EN          0x00008000
#define CR0_GPIO_22_EN          0x00004000
#define CR0_GPIO_23_EN          0x00002000
#define CR0_UART1_CTS_EN        0x00001000
#define CR0_UART1_DTR_EN        0x00000800
#define CR0_UART0_EXT_CLK       0x00000080
#define CR0_UART1_EXT_CLK       0x00000040
#define CR0_UART_DIV_MASK       0x0000003E


#define CR1_DET_MULT_EN         0x80000000
#define CR1_EXT_TIMER_EN        0x00800000


#define PSR_PLL_FWD_MASK        0xC0000000
#define PSR_PLL_FDBACK_MASK     0x30000000
#define PSR_PLL_TUNING_MASK     0x0E000000
#define PSR_PLB_CPU_MASK        0x01800000
#define PSR_OPB_PLB_MASK        0x00600000
#define PSR_PCI_PLB_MASK        0x00180000
#define PSR_EB_PLB_MASK         0x00060000
#define PSR_ROM_WIDTH_MASK      0x00018000
#define PSR_ROM_LOC             0x00004000
#define PSR_PCI_ASYNC_EN        0x00001000
#define PSR_PERCLK_SYNC         0x00000800     /* 405GPr only     */
#define PSR_PCI_ARBIT_EN        0x00000400
#define PSR_PLL_FWDA_BIT2       0x00000200     /* 405GPr only     */
#define PSR_PLL_FWDB_BIT2       0x00000100     /* 405GPr only     */
#define PSR_PLL_FDBACK_BIT2     0x00000080     /* 405GPr only     */
#define PSR_PLL_FDBACK_BIT3     0x00000040     /* 405GPr only     */
#define PSR_NEW_MODE            0x00000020     /* 405GPr only     */
#define PSR_FLIP_CIRC_DISABLE   0x00000010     /* 405GPr only     */

#define ECR_EMAC_RX_MASK        0xE0000000     /* 405GPr only     */
#define ECR_EMAC_RX_BYP         0x00000000     /* 405GPr only     */
#define ECR_EMAC_RX_1           0x20000000     /* 405GPr only     */
#define ECR_EMAC_RX_2           0x40000000     /* 405GPr only     */