📄 gt64260def.h
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#define CU_ARB_CTRL (0xf300)#define CU_CFG (0xb40c)#define CU_XBAR_TO (0xf304)#define CU_INT_CAUSE (0xf310)#define CU_INT_MASK (0xf314)#define CU_ERR_ADRS (0xf318)/* Ethernet Registers */#define ETH_PHY_ADRS (0x2000)#define ETH_SMIR (0x2010)#define ETH0_PCR (0x2400)#define ETH1_PCR (0x2800)#define ETH2_PCR (0x2c00)#define ETH0_PCXR (0x2408)#define ETH1_PCXR (0x2808)#define ETH2_PCXR (0x2c08)#define ETH0_PCMR (0x2410)#define ETH1_PCMR (0x2810)#define ETH2_PCMR (0x2c10)#define ETH0_PSR (0x2418)#define ETH1_PSR (0x2818)#define ETH2_PSR (0x2c18)#define ETH0_SPR (0x2420)#define ETH1_SPR (0x2820)#define ETH2_SPR (0x2c20)#define ETH0_HTPR (0x2428)#define ETH1_HTPR (0x2828)#define ETH2_HTPR (0x2c28)#define ETH0_FCSAL (0x2430)#define ETH1_FCSAL (0x2830)#define ETH2_FCSAL (0x2c30)#define ETH0_FCSAH (0x2438)#define ETH1_FCSAH (0x2838)#define ETH2_FCSAH (0x2c38)#define ETH0_SDCR (0x2440)#define ETH1_SDCR (0x2840)#define ETH2_SDCR (0x2c40)#define ETH0_SDCMR (0x2448)#define ETH1_SDCMR (0x2848)#define ETH2_SDCMR (0x2c48)#define ETH0_ICR (0x2450)#define ETH1_ICR (0x2850)#define ETH2_ICR (0x2c50)#define ETH0_IMR (0x2458)#define ETH1_IMR (0x2858)#define ETH2_IMR (0x2c58)/* MPSC Registers */#define MPSC_MRR (0xb400)#define MPSC_RCRR (0xb404)#define MPSC_TCRR (0xb408)#define MPSC_MMCRL0 (0x8000)#define MPSC_MMCRL1 (0x9000)#define MPSC_MMCRH0 (0x8004)#define MPSC_MMCRH1 (0x9004)#define MPSC0_CH0R2 (0x8010)#define MPSC1_CH1R2 (0x9010)#define MPSC0_INT_CAUSE (0xb804)#define MPSC0_INT_MASK (0xb884)#define MPSC1_INT_CAUSE (0xb80c)#define MPSC1_INT_MASK (0xb88c)/* SDMA Registers */#define SDC0 (0x4000)#define SDCM0 (0x4008)#define SCRDP0 (0x4810)#define SCTDP0 (0x4c10)#define SFTDP0 (0x4c14)#define SDC1 (0x6000)#define SDCM1 (0x6008)#define SCRDP1 (0x6810)#define SCTDP1 (0x6c10)#define SFTDP1 (0x6c14)#define SDMA_INT_CAUSE (0xb800)#define SDMA_INT_MASK (0xb880)/* BRG Registers */#define BRG_BCR0 (0xb200)#define BRG_BTR0 (0xb204)#define BRG_BCR1 (0xb208)#define BRG_BTR1 (0xb20c)#define BRG_BCR2 (0xb210)#define BRG_BTR2 (0xb214)#define BRG_INT_CAUSE (0xb834)#define BRG_INT_MASK (0xb8b4)/* Watchdog Timer register */#define WDC (0xb410)/* GPP Unit */#define GPP_IO_CTRL (0xf100) #define GPP_LVL_CTRL (0xf110) #define GPP_VAL (0xf104) #define GPP_INT_CAUSE (0xf108) #define GPP_INT_MASK (0xf10c) /* MPP Unit */#define MPP_CTRL0 (0xf000) #define MPP_CTRL1 (0xf004) #define MPP_CTRL2 (0xf008) #define MPP_CTRL3 (0xf00c) #define MPP_SP_MUX (0xf010) /* I2C registers */#define I2C_SLV_ADRS (0xc000)#define I2C_EXT_SLV_ADRS (0xc010)#define I2C_DATA (0xc004)#define I2C_CTRL (0xc008)#define I2C_STAT_BAUD (0xc00c)#define I2C_RESET (0xc01c)/* PCI *internal* register offsets */#define PCI0_SCS0_BAR_SZ (0xc08)#define PCI0_SCS1_BAR_SZ (0xd08)#define PCI0_SCS2_BAR_SZ (0xc0c)#define PCI0_SCS3_BAR_SZ (0xd0c)#define PCI0_CS0_BAR_SZ (0xc10)#define PCI0_CS1_BAR_SZ (0xd10)#define PCI0_CS2_BAR_SZ (0xd18)#define PCI0_CS3_BAR_SZ (0xc14)#define PCI0_BOOT_CS_BAR_SZ (0xd14)#define PCI0_P2P_MEM0_BAR_SZ (0xd1c)#define PCI0_P2P_MEM1_BAR_SZ (0xd20)#define PCI0_P2P_IO_BAR_SZ (0xd24)#define PCI0_CPU_BAR_SZ (0xd28)#define PCI0_DAC_SCS0_BAR_SZ (0xe00)#define PCI0_DAC_SCS1_BAR_SZ (0xe04)#define PCI0_DAC_SCS2_BAR_SZ (0xe08)#define PCI0_DAC_SCS3_BAR_SZ (0xe0c)#define PCI0_DAC_CS0_BAR_SZ (0xe10)#define PCI0_DAC_CS1_BAR_SZ (0xe14)#define PCI0_DAC_CS2_BAR_SZ (0xe18)#define PCI0_DAC_CS3_BAR_SZ (0xe1c)#define PCI0_DAC_BOOT_CS_BAR_SZ (0xe20)#define PCI0_DAC_P2P_MEM0_BAR_SZ (0xe24)#define PCI0_DAC_P2P_MEM1_BAR_SZ (0xe28)#define PCI0_DAC_CPU_BAR_SZ (0xe2c)#define PCI0_EXP_ROM_BAR_SZ (0xd2c)#define PCI0_BAR_EN (0xc3c)#define PCI0_SCS0_BAR_REMAP (0xc48)#define PCI0_SCS1_BAR_REMAP (0xd48)#define PCI0_SCS2_BAR_REMAP (0xc4c)#define PCI0_SCS3_BAR_REMAP (0xd4c)#define PCI0_CS0_BAR_REMAP (0xc50)#define PCI0_CS1_BAR_REMAP (0xd50)#define PCI0_CS2_BAR_REMAP (0xd58)#define PCI0_CS3_BAR_REMAP (0xc54)#define PCI0_BOOT_CS_ADRS_REMAP (0xd54)#define PCI0_P2P_MEM0_BAR_REMAP_L (0xd5c)#define PCI0_P2P_MEM0_BAR_REMAP_H (0xd60)#define PCI0_P2P_MEM1_BAR_REMAP_L (0xd64)#define PCI0_P2P_MEM1_BAR_REMAP_H (0xd68)#define PCI0_P2P_IO_BAR_REMAP (0xd6c)#define PCI0_CPU_BAR_REMAP (0xd70)#define PCI0_DAC_SCS0_BAR_REMAP (0xf00)#define PCI0_DAC_SCS1_BAR_REMAP (0xf04)#define PCI0_DAC_SCS2_BAR_REMAP (0xf08)#define PCI0_DAC_SCS3_BAR_REMAP (0xf0c)#define PCI0_DAC_CS0_BAR_REMAP (0xf10)#define PCI0_DAC_CS1_BAR_REMAP (0xf14)#define PCI0_DAC_CS2_BAR_REMAP (0xf18)#define PCI0_DAC_CS3_BAR_REMAP (0xf1c)#define PCI0_DAC_BOOTCS_BAR_REMAP (0xf20)#define PCI0_DAC_P2P_MEM0_BAR_REMAP_L (0xf24)#define PCI0_DAC_P2P_MEM0_BAR_REMAP_H (0xf28)#define PCI0_DAC_P2P_MEM1_BAR_REMAP_L (0xf2c)#define PCI0_DAC_P2P_MEM1_BAR_REMAP_H (0xf30)#define PCI0_DAC_CPU_BAR_REMAP (0xf34)#define PCI0_EXP_ROM_BAR_REMAP (0xf38)#define PCI0_ADRS_DECODE_CTRL (0xd3c)#define PCI0_CMD (0xc00)#define PCI0_MODE (0xd00)#define PCI0_TO_RETRY (0xc04)#define PCI0_RD_BUF_DISC_TMR (0xd04)#define PCI0_MSI_TRIG_TMR (0xc38)#define PCI0_ARB_CTRL (0x1d00)#define PCI0_IF_XBAR_CTRL_L (0x1d08)#define PCI0_IF_XBAR_CTRL_H (0x1d0c)#define PCI0_IF_XBAR_TO (0x1d04)#define PCI0_RD_RESP_XBAR_CTRL_L (0x1d18)#define PCI0_RD_RESP_XBAR_CTRL_H (0x1d1c)#define PCI0_SYNC_BAR_REG (0x1d10)#define PCI0_P2P_CONFIG (0x1d14)#define PCI0_SWAP_CTRL (0x1dd4)#define PCI0_ACC_CTRL_BASE0_L (0x1e00)#define PCI0_ACC_CTRL_BASE0_H (0x1e04)#define PCI0_ACC_CTRL_TOP0 (0x1e08)#define PCI0_ACC_CTRL_BASE1_L (0x1e10)#define PCI0_ACC_CTRL_BASE1_H (0x1e14)#define PCI0_ACC_CTRL_TOP1 (0x1e18)#define PCI0_ACC_CTRL_BASE2_L (0x1e20)#define PCI0_ACC_CTRL_BASE2_H (0x1e24)#define PCI0_ACC_CTRL_TOP2 (0x1e28)#define PCI0_ACC_CTRL_BASE3_L (0x1e30)#define PCI0_ACC_CTRL_BASE3_H (0x1e34)#define PCI0_ACC_CTRL_TOP3 (0x1e38)#define PCI0_ACC_CTRL_BASE4_L (0x1e40)#define PCI0_ACC_CTRL_BASE4_H (0x1e44)#define PCI0_ACC_CTRL_TOP4 (0x1e48)#define PCI0_ACC_CTRL_BASE5_L (0x1e50)#define PCI0_ACC_CTRL_BASE5_H (0x1e54)#define PCI0_ACC_CTRL_TOP5 (0x1e58)#define PCI0_ACC_CTRL_BASE6_L (0x1e60)#define PCI0_ACC_CTRL_BASE6_H (0x1e64)#define PCI0_ACC_CTRL_TOP6 (0x1e68)#define PCI0_ACC_CTRL_BASE7_L (0x1e70)#define PCI0_ACC_CTRL_BASE7_H (0x1e74)#define PCI0_ACC_CTRL_TOP7 (0x1e78)#define PCI1_SCS0_BAR_SZ (0xc88)#define PCI1_SCS1_BAR_SZ (0xd88)#define PCI1_SCS2_BAR_SZ (0xc8c)#define PCI1_SCS3_BAR_SZ (0xd8c)#define PCI1_CS0_BAR_SZ (0xc90)#define PCI1_CS1_BAR_SZ (0xd90)#define PCI1_CS2_BAR_SZ (0xd98)#define PCI1_CS3_BAR_SZ (0xc94)#define PCI1_BOOT_CS_BAR_SZ (0xd94)#define PCI1_P2P_MEM0_BAR_SZ (0xd9c)#define PCI1_P2P_MEM1_BAR_SZ (0xda0)#define PCI1_P2P_IO_BAR_SZ (0xda4)#define PCI1_CPU_BAR_SZ (0xda8)#define PCI1_DAC_SCS0_BAR_SZ (0xe80)#define PCI1_DAC_SCS1_BAR_SZ (0xe84)#define PCI1_DAC_SCS2_BAR_SZ (0xe88)#define PCI1_DAC_SCS3_BAR_SZ (0xe8c)#define PCI1_DAC_CS0_BAR_SZ (0xe90)#define PCI1_DAC_CS1_BAR_SZ (0xe94)#define PCI1_DAC_CS2_BAR_SZ (0xe98)#define PCI1_DAC_CS3_BAR_SZ (0xe9c)#define PCI1_DAC_BOOT_CS_BAR_SZ (0xea0)#define PCI1_DAC_P2P_MEM0_BAR_SZ (0xea4)#define PCI1_DAC_P2P_MEM1_BAR_SZ (0xea8)#define PCI1_DAC_CPU_BAR_SZ (0xeac)#define PCI1_EXP_ROM_BAR_SZ (0xdac)#define PCI1_BAR_EN (0xcbc)#define PCI1_SCS0_BAR_REMAP (0xcc8)#define PCI1_SCS1_BAR_REMAP (0xdd0)#define PCI1_SCS2_BAR_REMAP (0xccc)#define PCI1_SCS3_BAR_REMAP (0xdcc)#define PCI1_CS0_BAR_REMAP (0xcd0)#define PCI1_CS1_BAR_REMAP (0xdd0)#define PCI1_CS2_BAR_REMAP (0xdd8)#define PCI1_CS3_BAR_REMAP (0xcd4)#define PCI1_BOOT_CS_ADRS_REMAP (0xdd4)#define PCI1_P2P_MEM0_BAR_REMAP_L (0xddc)#define PCI1_P2P_MEM0_BAR_REMAP_H (0xde0)#define PCI1_P2P_MEM1_BAR_REMAP_L (0xde4)#define PCI1_P2P_MEM1_BAR_REMAP_H (0xde8)#define PCI1_P2P_IO_BAR_REMAP (0xdec)#define PCI1_CPU_BAR_REMAP (0xdf0)#define PCI1_DAC_SCS0_BAR_REMAP (0xf80)#define PCI1_DAC_SCS1_BAR_REMAP (0xf84)#define PCI1_DAC_SCS2_BAR_REMAP (0xf88)#define PCI1_DAC_SCS3_BAR_REMAP (0xf8c)#define PCI1_DAC_CS0_BAR_REMAP (0xf90)#define PCI1_DAC_CS1_BAR_REMAP (0xf94)#define PCI1_DAC_CS2_BAR_REMAP (0xf98)#define PCI1_DAC_CS3_BAR_REMAP (0xf9c)#define PCI1_DAC_BOOTCS_BAR_REMAP (0xfa0)#define PCI1_DAC_P2P_MEM0_BAR_REMAP_L (0xfa4)#define PCI1_DAC_P2P_MEM0_BAR_REMAP_H (0xfa8)#define PCI1_DAC_P2P_MEM1_BAR_REMAP_L (0xfac)#define PCI1_DAC_P2P_MEM1_BAR_REMAP_H (0xfb0)#define PCI1_DAC_CPU_BAR_REMAP (0xfb4)#define PCI1_EXP_ROM_BAR_REMAP (0xfb8)#define PCI1_ADRS_DECODE_CTRL (0xdbc)#define PCI1_CMD (0xc80)#define PCI1_MODE (0xd80)#define PCI1_TO_RETRY (0xc84)#define PCI1_RD_BUF_DISC_TMR (0xd84)#define PCI1_MSI_TRIG_TMR (0xcb8)#define PCI1_ARB_CTRL (0x1d80)#define PCI1_IF_XBAR_CTRL_L (0x1d88)#define PCI1_IF_XBAR_CTRL_H (0x1d8c)#define PCI1_IF_XBAR_TO (0x1d84)#define PCI1_RD_RESP_XBAR_CTRL_L (0x1d98)#define PCI1_RD_RESP_XBAR_CTRL_H (0x1d9c)#define PCI1_SYNC_BAR_REG (0x1d90)#define PCI1_P2P_CONFIG (0x1d94)#define PCI1_SWAP_CTRL (0x1d54)#define PCI1_ACC_CTRL_BASE0_L (0x1e80)#define PCI1_ACC_CTRL_BASE0_H (0x1e84)#define PCI1_ACC_CTRL_TOP0 (0x1e88)#define PCI1_ACC_CTRL_BASE1_L (0x1e90)#define PCI1_ACC_CTRL_BASE1_H (0x1e94)#define PCI1_ACC_CTRL_TOP1 (0x1e98)#define PCI1_ACC_CTRL_BASE2_L (0x1ea0)#define PCI1_ACC_CTRL_BASE2_H (0x1ea4)#define PCI1_ACC_CTRL_TOP2 (0x1ea8)#define PCI1_ACC_CTRL_BASE3_L (0x1eb0)#define PCI1_ACC_CTRL_BASE3_H (0x1eb4)#define PCI1_ACC_CTRL_TOP3 (0x1eb8)#define PCI1_ACC_CTRL_BASE4_L (0x1ec0)#define PCI1_ACC_CTRL_BASE4_H (0x1ec4)#define PCI1_ACC_CTRL_TOP4 (0x1ec8)#define PCI1_ACC_CTRL_BASE5_L (0x1ed0)#define PCI1_ACC_CTRL_BASE5_H (0x1ed4)#define PCI1_ACC_CTRL_TOP5 (0x1ed8)#define PCI1_ACC_CTRL_BASE6_L (0x1ee0)#define PCI1_ACC_CTRL_BASE6_H (0x1ee4)#define PCI1_ACC_CTRL_TOP6 (0x1ee8)#define PCI1_ACC_CTRL_BASE7_L (0x1ef0)#define PCI1_ACC_CTRL_BASE7_H (0x1ef4)#define PCI1_ACC_CTRL_TOP7 (0x1ef8)#define PCI0_SERR_ERR_MASK (0x0c28)#define PCI1_SERR_ERR_MASK (0x0ca8)#define PCI0_INT_CAUSE (0x1d58)#define PCI1_INT_CAUSE (0x1dd8)#define PCI0_ERR_MASK (0x1d5c)#define PCI1_ERR_MASK (0x1ddc)/* PCI_0 is the host card via CPCI interface */#define PCI0_CFG_ADRS (0xcf8)#define PCI0_CFG_DATA (0xcfc)/* PCI_1 is the local board PCI interface */#define PCI1_CFG_ADRS (0xc78)#define PCI1_CFG_DATA (0xc7c)/* PCI configuration register offsets *//* Function 0 *//* Function 1 *//* Function 2 *//* Function 3 *//* Function 4 *//* Function 5 *//* Function 6 *//* Function 7 *//* PCI Command Register. */#define PCICMD_ADDR 0x04#define PCICMD_FAST_B2B (1 << 9)#define PCICMD_SERR (1 << 8)#define PCICMD_PER (1 << 6)#define PCICMD_MEM_W_INV (1 << 4)#define PCICMD_SPECIAL_CYC (1 << 3)#define PCICMD_BUS_MASTER (1 << 2)#define PCICMD_MEM_SPACE (1 << 1)#define PCICMD_IO_SPACE (1 << 0)#define PCICMD_RSVD_MASK 0xFCA0/* PCI Status Register */#define PCISTATUS_ADDR 0x06#define PCISTATUS_DET_PE (1 << 15)#define PCISTATUS_SIG_SI (1 << 14)#define PCISTATUS_RCV_MA (1 << 13)#define PCISTATUS_RCV_TA (1 << 12)#define PCISTATUS_SIG_TA (1 << 11)#define PCISTATUS_DEVSEL_TIME (3 << 9)#define PCISTATUS_DATA_PE (1 << 8)#define PCISTATUS_FAST_B2BC (1 << 7)#define PCISTATUS_66MHZ_CAP (1 << 5)#define PCISTATUS_RSVD_MASK 0xFF4F#ifdef __cplusplus}#endif#endif /* __INCgt64260Defh */⌨️ 快捷键说明
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