📄 gt64260def.h
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/* gt64260Def.h - Motorola MPC107 definitions *//* Copyright 1984-2002 Wind River Systems, Inc. *//*modification history--------------------01a,24apr02,gtf created*//*DESCRIPTION:Contains structure typedefs and constants for the Marvell Galileo GT64260.*/#ifndef __INCgt64260Defh#define __INCgt64260Defh#ifdef __cplusplusextern "C" {#endif/* HI/LOW Adjust Macros; generic, tool vendor neutral. */#define HI_HALF(value) ((value >> 16) & 0x0000FFFF)#define LO_HALF(value) (value & 0x0000FFFF)#define GT64260_REG_RD(x,val) \ { \ UINT32 tmp ; \ tmp = *((UINT32*)(GT64260_BASE_ADRS+(x))); \ EIEIO ; \ (*val) = LONGSWAP(tmp); \ EIEIO ; \ }#define GT64260_REG_WR(x,val) \ { \ UINT32 tmp ; \ tmp = LONGSWAP(val); \ EIEIO ; \ *((UINT32*)(GT64260_BASE_ADRS+(x))) = tmp ; \ EIEIO ; \ } /* CPU interface registers */ /* CPU Address Decode Register Map */#define CPU_SCS0_DECODE_ADRS_L (0x008)#define CPU_SCS0_DECODE_ADRS_H (0x010)#define CPU_SCS1_DECODE_ADRS_L (0x208)#define CPU_SCS1_DECODE_ADRS_H (0x210)#define CPU_SCS2_DECODE_ADRS_L (0x018)#define CPU_SCS2_DECODE_ADRS_H (0x020)#define CPU_SCS3_DECODE_ADRS_L (0x218)#define CPU_SCS3_DECODE_ADRS_H (0x220)#define CPU_CS0_DECODE_ADRS_L (0x028)#define CPU_CS0_DECODE_ADRS_H (0x030)#define CPU_CS1_DECODE_ADRS_L (0x228)#define CPU_CS1_DECODE_ADRS_H (0x230)#define CPU_CS2_DECODE_ADRS_L (0x248)#define CPU_CS2_DECODE_ADRS_H (0x250)#define CPU_CS3_DECODE_ADRS_L (0x038)#define CPU_CS3_DECODE_ADRS_H (0x040)#define CPU_BOOT_CS_DECODE_ADRS_L (0x238)#define CPU_BOOT_CS_DECODE_ADRS_H (0x240)#define CPU_PCI0_IO_DECODE_ADRS_L (0x048)#define CPU_PCI0_IO_DECODE_ADRS_H (0x050)#define CPU_PCI0_MEM0_DECODE_ADRS_L (0x058)#define CPU_PCI0_MEM0_DECODE_ADRS_H (0x060)#define CPU_PCI0_MEM1_DECODE_ADRS_L (0x080)#define CPU_PCI0_MEM1_DECODE_ADRS_H (0x088)#define CPU_PCI0_MEM2_DECODE_ADRS_L (0x258)#define CPU_PCI0_MEM2_DECODE_ADRS_H (0x260)#define CPU_PCI0_MEM3_DECODE_ADRS_L (0x280)#define CPU_PCI0_MEM3_DECODE_ADRS_H (0x288)#define CPU_PCI1_IO_DECODE_ADRS_L (0x090)#define CPU_PCI1_IO_DECODE_ADRS_H (0x098)#define CPU_PCI1_MEM0_DECODE_ADRS_L (0x0a0)#define CPU_PCI1_MEM0_DECODE_ADRS_H (0x0a8)#define CPU_PCI1_MEM1_DECODE_ADRS_L (0x0b0)#define CPU_PCI1_MEM1_DECODE_ADRS_H (0x0b8)#define CPU_PCI1_MEM2_DECODE_ADRS_L (0x2a0)#define CPU_PCI1_MEM2_DECODE_ADRS_H (0x2a8)#define CPU_PCI1_MEM3_DECODE_ADRS_L (0x2b0)#define CPU_PCI1_MEM3_DECODE_ADRS_H (0x2b8)#define CPU_INT_SPC_DECODE_ADRS (0x068)#define CPU0_DECODE_ADRS_L (0x290)#define CPU0_DECODE_ADRS_H (0x298)#define CPU1_DECODE_ADRS_L (0x2c0)#define CPU1_DECODE_ADRS_H (0x2c8)#define CPU_PCI0_IO_ADRS_REMAP (0x0f0)#define CPU_PCI0_MEM0_ADRS_REMAP_L (0x0f8)#define CPU_PCI0_MEM0_ADRS_REMAP_H (0x320)#define CPU_PCI0_MEM1_ADRS_REMAP_L (0x100)#define CPU_PCI0_MEM1_ADRS_REMAP_H (0x328)#define CPU_PCI0_MEM2_ADRS_REMAP_L (0x2f8)#define CPU_PCI0_MEM2_ADRS_REMAP_H (0x330)#define CPU_PCI0_MEM3_ADRS_REMAP_L (0x300)#define CPU_PCI0_MEM3_ADRS_REMAP_H (0x338)#define CPU_PCI1_IO_ADRS_REMAP (0x108)#define CPU_PCI1_MEM0_ADRS_REMAP_L (0x110)#define CPU_PCI1_MEM0_ADRS_REMAP_H (0x340)#define CPU_PCI1_MEM1_ADRS_REMAP_L (0x118)#define CPU_PCI1_MEM1_ADRS_REMAP_H (0x348)#define CPU_PCI1_MEM2_ADRS_REMAP_L (0x310)#define CPU_PCI1_MEM2_ADRS_REMAP_H (0x350)#define CPU_PCI1_MEM3_ADRS_REMAP_L (0x318)#define CPU_PCI1_MEM3_ADRS_REMAP_H (0x358)/* CPU control register map */#define CPU_CFG (0x000)#define CPU_MODE (0x120)#define CPU_MASTER_CTRL (0x160)#define CPU_IF_XBAR_CTRL_L (0x150)#define CPU_IF_XBAR_CTRL_H (0x158)#define CPU_IF_XBAR_TO (0x168)#define CPU_RD_RESP_XBAR_CTRL_L (0x170)#define CPU_RD_RESP_XBAR_CTRL_H (0x178)/* CPU sync barrier register map */#define CPU_PCI0_SYNC_BARRIER (0x0c0)#define CPU_PCI1_SYNC_BARRIER (0x0c8)/* CPU Access Protection Register Map */#define CPU_PROTECT_ADRS0_L (0x180)#define CPU_PROTECT_ADRS0_H (0x188)#define CPU_PROTECT_ADRS1_L (0x190)#define CPU_PROTECT_ADRS1_H (0x198)#define CPU_PROTECT_ADRS2_L (0x1a0)#define CPU_PROTECT_ADRS2_H (0x1a8)#define CPU_PROTECT_ADRS3_L (0x1b0)#define CPU_PROTECT_ADRS3_H (0x1b8)#define CPU_PROTECT_ADRS4_L (0x1c0)#define CPU_PROTECT_ADRS4_H (0x1c8)#define CPU_PROTECT_ADRS5_L (0x1d0)#define CPU_PROTECT_ADRS5_H (0x1d8)#define CPU_PROTECT_ADRS6_L (0x1e0)#define CPU_PROTECT_ADRS6_H (0x1e8)#define CPU_PROTECT_ADRS7_L (0x1f0)#define CPU_PROTECT_ADRS7_H (0x1f8)/* Snoop control register map */#define CPU_SNOOP_BASE_ADRS0 (0x380)#define CPU_SNOOP_TOP_ADRS0 (0x388)#define CPU_SNOOP_BASE_ADRS1 (0x390)#define CPU_SNOOP_TOP_ADRS1 (0x398)#define CPU_SNOOP_BASE_ADRS2 (0x3a0)#define CPU_SNOOP_TOP_ADRS2 (0x3a8)#define CPU_SNOOP_BASE_ADRS3 (0x3b0)#define CPU_SNOOP_TOP_ADRS3 (0x3b8)/* CPU error report register map */#define CPU_ERR_ADRS_L (0x070)#define CPU_ERR_ADRS_H (0x078)#define CPU_ERR_DATA_L (0x128)#define CPU_ERR_DATA_H (0x130)#define CPU_ERR_PARITY (0x138)#define CPU_ERR_CAUSE (0x140)#define CPU_ERR_MASK (0x148)/* SDRAM controller registers */#define SDRAM_CFG (0x448)#define SDRAM_MODE (0x474)#define SDRAM_ADRS_CTRL (0x47c)#define SDRAM_TIM_PARMS (0x4b4)#define SDRAM_UMA_CTRL (0x4a4)#define SDRAM_IF_XBAR_CTRL_L (0x4a8)#define SDRAM_IF_XBAR_CTRL_H (0x4ac)#define SDRAM_IF_XBAR_TO (0x4b0)#define SDRAM_BANK0 (0x44c)#define SDRAM_BANK1 (0x450)#define SDRAM_BANK2 (0x454)#define SDRAM_BANK3 (0x458)#define SDRAM_ERR_DATA_L (0x484)#define SDRAM_ERR_DATA_H (0x480)#define SDRAM_ERR_ADRS (0x490)#define SDRAM_RX_ECC (0x488)#define SDRAM_CALC_ECC (0x48c)#define SDRAM_ECC_CTRL (0x494)#define SDRAM_ECC_ERR_CTR (0x498)/* Device controller registers */#define DEVICE_BANK0 (0x45c)#define DEVICE_BANK1 (0x460)#define DEVICE_BANK2 (0x464)#define DEVICE_BANK3 (0x468)#define DEVICE_BOOT (0x46c)#define DEVICE_IF_CTRL (0x4c0)#define DEVICE_IF_XBAR_CTRL_L (0x4c8)#define DEVICE_IF_XBAR_CTRL_H (0x4cc)#define DEVICE_IF_XBAR_TO (0x4c4)#define DEVICE_INT_CAUSE (0x4d0)#define DEVICE_INT_MASK (0x4d4)#define DEVICE_ERR_ADRS (0x4d8)/* Message Unit */#define MU_IN_MSG_REG0_PCI1 (0x1c90)#define MU_IN_MSG_REG0_PCI0 (0x1c10)#define MU_IN_MSG_REG1_PCI1 (0x1c94)#define MU_IN_MSG_REG1_PCI0 (0x1c14)#define MU_OUT_MSG_REG0_PCI1 (0x1c98)#define MU_OUT_MSG_REG0_PCI0 (0x1c18)#define MU_OUT_MSG_REG1_PCI1 (0x1c9c)#define MU_OUT_MSG_REG1_PCI0 (0x1c1c)#define MU_IN_DB_REG_PCI1 (0x1ca0)#define MU_IN_DB_REG_PCI0 (0x1c20)#define MU_IN_INT_CAUSE_PCI1 (0x1ca4)#define MU_IN_INT_CAUSE_PCI0 (0x1c24)#define MU_IN_INT_MASK_PCI1 (0x1ca8)#define MU_IN_INT_MASK_PCI0 (0x1c28)#define MU_OUT_DB_REG_PCI1 (0x1cac)#define MU_OUT_DB_REG_PCI0 (0x1c2c)#define MU_OUT_INT_CAUSE_PCI1 (0x1cb0)#define MU_OUT_INT_CAUSE_PCI0 (0x1c30)#define MU_OUT_INT_MASK_PCI1 (0x1cb4)#define MU_OUT_INT_MASK_PCI0 (0x1c34)#define MU_IN_QUEUE_PORT_PCI1 (0x1cc0)#define MU_IN_QUEUE_PORT_PCI0 (0x1c40)#define MU_OUT_QUEUE_PORT_PCI1 (0x1cc4)#define MU_OUT_QUEUE_PORT_PCI0 (0x1c44)#define MU_QUEUE_CTRL_PCI1 (0x1cd0)#define MU_QUEUE_CTRL_PCI0 (0x1c50)#define MU_QUEUE_BASE_ADRS_PCI1 (0x1cd4)#define MU_QUEUE_BASE_ADRS_PCI0 (0x1c54)#define MU_IN_FREE_HD_PTR_PCI1 (0x1ce0)#define MU_IN_FREE_HD_PTR_PCI0 (0x1c60)#define MU_IN_FREE_TL_PTR_PCI1 (0x1ce4)#define MU_IN_FREE_TL_PTR_PCI0 (0x1c64)#define MU_IN_POST_HD_PTR_PCI1 (0x1ce8)#define MU_IN_POST_HD_PTR_PCI0 (0x1c68)#define MU_IN_POST_TL_PTR_PCI1 (0x1cec)#define MU_IN_POST_TL_PTR_PCI0 (0x1c6c)#define MU_OUT_FREE_HD_PTR_PCI1 (0x1cf0)#define MU_OUT_FREE_HD_PTR_PCI0 (0x1c70)#define MU_OUT_FREE_TL_PTR_PCI1 (0x1cf4)#define MU_OUT_FREE_TL_PTR_PCI0 (0x1c74)#define MU_OUT_POST_HD_PTR_PCI1 (0x1cf8)#define MU_OUT_POST_HD_PTR_PCI0 (0x1c78)#define MU_OUT_POST_TL_PTR_PCI1 (0x1cfc)#define MU_OUT_POST_TL_PTR_PCI0 (0x1c7c)/* IDMA Unit registers */#define DMA_CH0_DMA_BYTE_CNT (0x800)#define DMA_CH1_DMA_BYTE_CNT (0x804)#define DMA_CH2_DMA_BYTE_CNT (0x808)#define DMA_CH3_DMA_BYTE_CNT (0x80c)#define DMA_CH4_DMA_BYTE_CNT (0x900)#define DMA_CH5_DMA_BYTE_CNT (0x904)#define DMA_CH6_DMA_BYTE_CNT (0x908)#define DMA_CH7_DMA_BYTE_CNT (0x90c)#define DMA_CH0_DMA_SRC_ADRS (0x810)#define DMA_CH1_DMA_SRC_ADRS (0x814)#define DMA_CH2_DMA_SRC_ADRS (0x818)#define DMA_CH3_DMA_SRC_ADRS (0x81c)#define DMA_CH4_DMA_SRC_ADRS (0x910)#define DMA_CH5_DMA_SRC_ADRS (0x914)#define DMA_CH6_DMA_SRC_ADRS (0x918)#define DMA_CH7_DMA_SRC_ADRS (0x91c)#define DMA_CH0_DMA_DST_ADRS (0x820)#define DMA_CH1_DMA_DST_ADRS (0x824)#define DMA_CH2_DMA_DST_ADRS (0x828)#define DMA_CH3_DMA_DST_ADRS (0x82c)#define DMA_CH4_DMA_DST_ADRS (0x920)#define DMA_CH5_DMA_DST_ADRS (0x924)#define DMA_CH6_DMA_DST_ADRS (0x928)#define DMA_CH7_DMA_DST_ADRS (0x92c)#define DMA_CH0_NEXT_DESC_PTR (0x830)#define DMA_CH1_NEXT_DESC_PTR (0x834)#define DMA_CH2_NEXT_DESC_PTR (0x838)#define DMA_CH3_NEXT_DESC_PTR (0x83c)#define DMA_CH4_NEXT_DESC_PTR (0x930)#define DMA_CH5_NEXT_DESC_PTR (0x934)#define DMA_CH6_NEXT_DESC_PTR (0x938)#define DMA_CH7_NEXT_DESC_PTR (0x93c)#define DMA_CH0_CURR_DESC_PTR (0x870)#define DMA_CH1_CURR_DESC_PTR (0x874)#define DMA_CH2_CURR_DESC_PTR (0x878)#define DMA_CH3_CURR_DESC_PTR (0x87c)#define DMA_CH4_CURR_DESC_PTR (0x970)#define DMA_CH5_CURR_DESC_PTR (0x974)#define DMA_CH6_CURR_DESC_PTR (0x978)#define DMA_CH7_CURR_DESC_PTR (0x97c)#define DMA_CH0_SRC_PCI_ADRS_H (0x890)#define DMA_CH1_SRC_PCI_ADRS_H (0x894)#define DMA_CH2_SRC_PCI_ADRS_H (0x898)#define DMA_CH3_SRC_PCI_ADRS_H (0x89c)#define DMA_CH4_SRC_PCI_ADRS_H (0x990)#define DMA_CH5_SRC_PCI_ADRS_H (0x994)#define DMA_CH6_SRC_PCI_ADRS_H (0x998)#define DMA_CH7_SRC_PCI_ADRS_H (0x99c)#define DMA_CH0_DST_PCI_ADRS_H (0x8a0)#define DMA_CH1_DST_PCI_ADRS_H (0x8a4)#define DMA_CH2_DST_PCI_ADRS_H (0x8a8)#define DMA_CH3_DST_PCI_ADRS_H (0x8ac)#define DMA_CH4_DST_PCI_ADRS_H (0x9a0)#define DMA_CH5_DST_PCI_ADRS_H (0x9a4)#define DMA_CH6_DST_PCI_ADRS_H (0x9a8)#define DMA_CH7_DST_PCI_ADRS_H (0x9ac)#define DMA_CH0_NEXT_DESC_PCI_H (0x8b0)#define DMA_CH1_NEXT_DESC_PCI_H (0x8b4)#define DMA_CH2_NEXT_DESC_PCI_H (0x8b8)#define DMA_CH3_NEXT_DESC_PCI_H (0x8bc)#define DMA_CH4_NEXT_DESC_PCI_H (0x9b0)#define DMA_CH5_NEXT_DESC_PCI_H (0x9b4)#define DMA_CH6_NEXT_DESC_PCI_H (0x9b8)#define DMA_CH7_NEXT_DESC_PCI_H (0x9bc)#define DMA_CH0_CTRL_L (0x840)#define DMA_CH0_CTRL_H (0x880)#define DMA_CH1_CTRL_L (0x844)#define DMA_CH1_CTRL_H (0x884)#define DMA_CH2_CTRL_L (0x848)#define DMA_CH2_CTRL_H (0x888)#define DMA_CH3_CTRL_L (0x84c)#define DMA_CH3_CTRL_H (0x88c)#define DMA_CH4_CTRL_L (0x940)#define DMA_CH4_CTRL_H (0x980)#define DMA_CH5_CTRL_L (0x944)#define DMA_CH5_CTRL_H (0x984)#define DMA_CH6_CTRL_L (0x948)#define DMA_CH6_CTRL_H (0x988)#define DMA_CH7_CTRL_L (0x94c)#define DMA_CH7_CTRL_H (0x98c)#define DMA_CH0_3_ARB_CTRL (0x860)#define DMA_CH4_7_ARB_CTRL (0x960)#define DMA_CH0_3_XBAR_TO (0x8d0)#define DMA_CH4_7_XBAR_TO (0x9d0)#define DMA_CH0_3_INT_CAUSE (0x8c0)#define DMA_CH0_3_INT_MASK (0x8c4)#define DMA_CH0_3_ERR_ADRS (0x8c8)#define DMA_CH0_3_ERR_SEL (0x8cc)#define DMA_CH4_7_INT_CAUSE (0x9c0)#define DMA_CH4_7_INT_MASK (0x9c4)#define DMA_CH4_7_ERR_ADRS (0x9c8)#define DMA_CH4_7_ERR_SEL (0x9cc)/* Timer / counter registers */#define TMR_CTR_0 (0x850)#define TMR_CTR_1 (0x854)#define TMR_CTR_2 (0x858)#define TMR_CTR_3 (0x85c)#define TMR_CTR_4 (0x950)#define TMR_CTR_5 (0x954)#define TMR_CTR_6 (0x958)#define TMR_CTR_7 (0x95c)#define TMR0_3_CTRL (0x864)#define TMR0_3_INT_CAUSE (0x868)#define TMR0_3_INT_MASK (0x86c)#define TMR4_7_CTRL (0x964)#define TMR4_7_INT_CAUSE (0x968)#define TMR4_7_INT_MASK (0x96c)/* Communications Unit */#define CU_ETH0_ADRS_CTRL_L (0xf200)#define CU_ETH0_ADRS_CTRL_H (0xf204)#define CU_ETH0_RX_BUFF_PCI_H (0xf208)#define CU_ETH0_TX_BUFF_PCI_H (0xf20c)#define CU_ETH0_RX_DESC_PCI_H (0xf210)#define CU_ETH0_TX_DESC_PCI_H (0xf214)#define CU_ETH0_HASH_TBL_PCI_H (0xf218)#define CU_ETH1_ADRS_CTRL_L (0xf220)#define CU_ETH1_ADRS_CTRL_H (0xf224)#define CU_ETH1_RX_BUFF_PCI_H (0xf228)#define CU_ETH1_TX_BUFF_PCI_H (0xf22c)#define CU_ETH1_RX_DESC_PCI_H (0xf230)#define CU_ETH1_TX_DESC_PCI_H (0xf234)#define CU_ETH1_HASH_TBL_PCI_H (0xf238)#define CU_ETH2_ADRS_CTRL_L (0xf240)#define CU_ETH2_ADRS_CTRL_H (0xf244)#define CU_ETH2_RX_BUFF_PCI_H (0xf248)#define CU_ETH2_TX_BUFF_PCI_H (0xf24c)#define CU_ETH2_RX_DESC_PCI_H (0xf250)#define CU_ETH2_TX_DESC_PCI_H (0xf254)#define CU_ETH2_HASH_TBL_PCI_H (0xf258)#define CU_MPSC0_ADRS_CTRL_L (0xf280)#define CU_MPSC0_ADRS_CTRL_H (0xf284)#define CU_MPSC0_RX_BUFF_PCI_H (0xf288)#define CU_MPSC0_TX_BUFF_PCI_H (0xf28c)#define CU_MPSC0_RX_DESC_PCI_H (0xf290)#define CU_MPSC0_TX_DESC_PCI_H (0xf294)#define CU_MPSC1_ADRS_CTRL_L (0xf2c0)#define CU_MPSC1_ADRS_CTRL_H (0xf2c4)#define CU_MPSC1_RX_BUFF_PCI_H (0xf2c8)#define CU_MPSC1_TX_BUFF_PCI_H (0xf2cc)#define CU_MPSC1_RX_DESC_PCI_H (0xf2d0)#define CU_MPSC1_TX_DESC_PCI_H (0xf2d4)#define CU_SER_INIT_PCI_H (0xf320)#define CU_SER_INIT_LST_DATA_H (0xf324)#define CU_SER_INIT_CTRL_H (0xf328)#define CU_SER_INIT_STAT_H (0xf32c)⌨️ 快捷键说明
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