sysgt64260pci.c

WINDRIVER SBC7410 BSP

/* sysGt64260Pci.c - Galileo GT64260 PCI routines */

/* Copyright 1995-2002 Wind River Systems. */

/*
modification history
--------------------
01b,23apr02,gtf modified from wrPpmc74xx bsp.
01a,12may01,g_h created
*/

/*
DESCRIPTION
Marvel Galileo GT64260 PCI driver for PCI-0 and PCI-1 interfaces.

INCLUDE FILES: sysGt64260Pci.h
*/


/* includes */

#include "vxWorks.h"
#include "config.h"
#include "memLib.h"

#include "sysGt64260Pci.h"

/* defines */

/* globals */

/* forward declarations */

/* externals */

/***************************************************************************
*
* sysGt64260PciInit - PCI setup for the GT64260
*
* This routine setups the GT64260 PCI unit. If mode
* is 0 then PCI-0 is setup. If mode is 1 then PCI-1
* is setup.
*
* RETURNS: N/A
*
* SEE ALSO: sysGt64260CfgWrite(), sysMpc107CfgRead()
*/

void sysGt64260PciInit
    (
    int mode
    )
    {
    UINT32 temp ;
    int pciBusNo ; 
    int pciDevNo ;
    int pciFuncNo ;

    /* SDRAM from the PCI bus */
    /* enable only SCS0 bar and internal memory mapped registers */
    if ( !mode )
        {
        GT64260_REG_WR(PCI0_BAR_EN, 0xfffffdfe);
        }
    else
        {
        GT64260_REG_WR(PCI1_BAR_EN, 0xfffffdfe);
        }

    /* Map PCI bus address 0 to local sdram address 0 */
    /* set size of SCS0 bar -> LOCAL_MEM_SIZE -> 256 MB, default config */
    if ( !mode )
        {
        GT64260_REG_WR(PCI0_SCS0_BAR_SZ, 0x0ffff000) ;
        }
    else
        {
        GT64260_REG_WR(PCI1_SCS0_BAR_SZ, 0x0ffff000) ;
        }

    /* SCS0 used, SCS1-3 not used - need to open up window to SCS0.
       No other PCI access to local resources is required. */

    /* set access properties on SCS0 as seen from the PCI bus */
    if ( !mode )
        {
        GT64260_REG_WR(PCI0_ACC_CTRL_BASE0_L, 0x00000100) ; /* prefetch enabled */
        GT64260_REG_WR(PCI0_ACC_CTRL_BASE0_H, 0) ;
        GT64260_REG_WR(PCI0_ACC_CTRL_TOP0, 0x000000ff);
        }
    else
        {
        GT64260_REG_WR(PCI1_ACC_CTRL_BASE0_L, 0x00000100) ; /* prefetch enabled */
        GT64260_REG_WR(PCI1_ACC_CTRL_BASE0_H, 0) ;
        GT64260_REG_WR(PCI1_ACC_CTRL_TOP0, 0x000000ff);
        }

    /* Disable combine on write[4], read multiple[9], combine on read[5], per
       errata... */
    if ( !mode )
        {
        GT64260_REG_RD(PCI0_CMD, &temp) ;
        temp &= ~0x330 ;
        temp |= 0xc0 ;
        GT64260_REG_WR(PCI0_CMD, temp) ;
        }
    else
        {
        GT64260_REG_RD(PCI1_CMD, &temp) ;
        temp &= ~0x330 ;
        temp |= 0xc0 ;
        GT64260_REG_WR(PCI1_CMD, temp) ;
        }

    /* NOTE: the 64260 arbiter should not be enabled there is an on-board
       external arbiter on the wrSbc7410 board. */

    /* set PCI-0/1 SCS[0] BAR, base at 0x0 */
    pciConfigOutLong(0,0,0,PCI_CFG_BASE_ADDRESS_0,0x00000004);

    /* set latency timer and cache line size */
    pciConfigOutByte (0,0,0, PCI_CFG_CACHE_LINE_SIZE, 0x08);
    pciConfigOutByte (0,0,0, PCI_CFG_LATENCY_TIMER, 0x40);

    /* enable the command register for PCI_0 or PCI_1  */
    pciConfigOutLong(0,0,0,PCI_CFG_COMMAND,0x00000007);


    if ( !mode )
        {
        /* In this mode the wrSbc7410 board is installed in a PCI backplane
           in the I/O expand unit. The 7410 still acts as a master of this PCI
           bus. The only difference is that it accesses PCI via PCI-0 and 
           goes through a 21154 chip to access the rest of the PCI bus. */

        /* Note that the 21154 cannot be configured until the pci-0 interface has
           been turned on, also note that there is an on-board arbiter for the pci-0
           bus. */

        /* Configure 21154 transparent bridge chip - program the 21154 to intercept access to
           pci i/o and mem space used by pci-1 to forward to secondary 
           side of 21154 to fei card on the other side. */

        /* Set bus number to secondary side of 21154 to be bus 1 with primary (local)
           side bus 0. The GT64260 will generate a type 1 access if the bus number
           is not 0 so the configuration access should get forwarded across the 21154. */

        if ( pciFindDevice(INTEL_21154_PCI_VENDOR_ID, INTEL_21154_PCI_DEVICE_ID, 0,
                           &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR )
            {
            /* ensure device is disabled */
            pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0x0000);

            /* primary cache line size */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_CACHE_LINE_SIZE, 0x08);

            /* primary latency timer */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, 0x40);

            /* primary bus no. */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PRIMARY_BUS, 0x00);

            /* secondary bus no. */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_SECONDARY_BUS, 0x01);

            /* subordinate bus no. */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_SUBORDINATE_BUS, 0x01);

            /* secondary latency timer */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_SEC_LATENCY, 0x40);

            /* I/O base address register */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IO_BASE, 0x00);

            /* I/O limit address register */
            pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IO_LIMIT, 0x00);

            /* Prefetchable memory base address register */
            pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PRE_MEM_BASE, 0x1200);

            /* Prefetchable memory limit address register */
            pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PRE_MEM_LIMIT, 0x13ff);

            /* Prefetchable Memory Base Address Upper 32 Bits Register鵒ffset 28h */
            pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PRE_MEM_BASE_U, 0x00000000);

            /* Prefetchable Memory Limit Address Upper 32 Bits Register鵒ffset 2Ch */
            pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PRE_MEM_LIMIT_U, 0x00000000);

            /* I/O Base Address Upper 16 Bits Register鵒ffset 30h */
            pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IO_BASE_U, 0x1000);

            /* I/O Limit Address Upper 16 Bits Register鵒ffset 32h */
            pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IO_LIMIT_U, 0x11ff);

            /* Bridge Control Register鵒ffset 3Eh */
            /* reset secondary bus */
            pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BRIDGE_CONTROL, 0x00040000);

            /* Enable the chip */
            pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0x0007);
            }
        else
            {
            sysLedSet(2,LED_ON);
            }
        }

    return;
    }


#ifdef INCLUDE_PCI_STANDALONE
#define PCI_CFG_ADRS 	PCI1_CFG_ADRS
#define PCI_CFG_DATA 	PCI1_CFG_DATA
#define PCI_INT_CAUSE 	PCI1_INT_CAUSE
#endif
#ifdef INCLUDE_PCI_CARD_IN_BACKPLANE
#define PCI_CFG_ADRS 	PCI0_CFG_ADRS
#define PCI_CFG_DATA 	PCI0_CFG_DATA
#define PCI_INT_CAUSE 	PCI0_INT_CAUSE
#endif
IMPORT void sysMsDelay(int delay);
/***************************************************************************
*
* sysPciConfigRead - perform configuration reads on the PCI-0 or PCI-1
* bus interface.
*
* RETURNS: OK, ERROR.
*
* SEE ALSO: 
*/
STATUS sysPciConfigRead
    (
    int bus, 
    int dev, 
    int func, 
    int reg, 
    int size, 
    void * pResult
    )
    {
    UINT32 data ;
    UINT32 adrs ;
    UINT8 *bResult = (UINT8*)pResult ;
    UINT16 *wResult = (UINT16*)pResult ;
    UINT32 *lResult = (UINT32*)pResult ;
    UINT32 temp ;

    /* reset master abort bit */

    GT64260_REG_RD(PCI_INT_CAUSE, &temp);
    temp &= ~0x00000100 ;
    GT64260_REG_WR(PCI_INT_CAUSE, temp );

    adrs = 0x80000000 | (bus&0xff)<<16 | (dev&0x1f)<<11 | (func&0x7)<<8 | (reg&0xfc) ;
    GT64260_REG_WR(PCI_CFG_ADRS, adrs);
    sysMsDelay(1);
    GT64260_REG_RD(PCI_CFG_DATA, &data);

#if defined(INCLUDE_PCI_CARD_IN_BACKPLANE)
    GT64260_REG_RD(CPU_PCI1_SYNC_BARRIER, &temp);
#endif
#if defined(INCLUDE_PCI_STANDALONE)
    GT64260_REG_RD(CPU_PCI0_SYNC_BARRIER, &temp);
#endif

    /* check read data and set to -1 if master abort bit is set */
    GT64260_REG_RD(PCI_INT_CAUSE, &temp);
    if ( (data != 0xffffffff) && (temp&0x00000100) )
        {
        data = 0xffffffff ;
        *lResult = data ;
        /* reset master abort bit */
        GT64260_REG_RD(PCI_INT_CAUSE, &temp);
        temp &= ~0x00000100 ;
        GT64260_REG_WR(PCI_INT_CAUSE, temp);
        return ERROR ;
        }

    switch ( size )
        {
        case 1:
            switch ( reg&03 )
                {
                case 0:
                    *bResult = (UINT8)((data & 0x000000ff) >> 0) ;
                    break;
                case 1:
                    *bResult = (UINT8)((data & 0x0000ff00) >> 8) ;
                    break;
                case 2:
                    *bResult    =    (   UINT8)(   (   data    &    0x00ff0000)    >>    16)    ;
                    break;
                case 3:
                    *bResult = (UINT8)((data & 0xff000000) >> 24) ;
                    break;
                }
            break;
        case 2:
            switch ( reg&02 )
                {
                case 0:
                    *wResult = (UINT16)((data & 0x0000ffff) >> 0) ;
                    break;
                case 2:
                    *wResult = (UINT16)((data & 0xffff0000) >> 16) ;
                    break;
                }
            break;
        case 4:
            if ( reg&0x3 )
                return ERROR;
            else
                *lResult = data ;
            break;
        default:
            return ERROR ;
        }
    return OK ;
    }

/***************************************************************************
*
* sysPciConfigWrite - perform configuration writes on the PCI-0 or PCI-1
* bus interface.
*
* RETURNS: OK, ERROR.
*
* SEE ALSO: 
*/
STATUS sysPciConfigWrite
    (
    int bus, 
    int dev, 
    int func, 
    int reg, 
    int size, 
    UINT32 data
    )
    {
    UINT32 adrs ;
    UINT8  bData = (data&0xff) ;
    UINT16 wData = (data&0xffff) ;
    UINT32 lData ;
    UINT32 temp ;

    adrs = 0x80000000 | (bus&0xff)<<16 | (dev&0x1f)<<11 | (func&0x7)<<8 | (reg&0xfc) ;
    GT64260_REG_WR(PCI_CFG_ADRS, adrs);
    sysMsDelay(1);
    GT64260_REG_RD(PCI_CFG_DATA, &lData);

#if defined(INCLUDE_PCI_CARD_IN_BACKPLANE)
    GT64260_REG_RD(CPU_PCI1_SYNC_BARRIER, &temp);
#endif
#if defined(INCLUDE_PCI_STANDALONE)
    GT64260_REG_RD(CPU_PCI0_SYNC_BARRIER, &temp);
#endif

    switch ( size )
        {
        case 1:
            switch ( reg&0x3 )
                {
                case 0:
                    lData |= (UINT32)(bData << 0) ;
                    break;
                case 1:
                    lData |= (UINT32)(bData << 8) ;
                    break;
                case 2:
                    lData |= (UINT32)(bData << 16) ;
                    break;
                case 3:
                    lData |= (UINT32)(bData << 24) ;
                    break;
                }
            break;
        case 2:
            switch ( reg&0x2 )
                {
                case 0:
                    lData |= (UINT32)(wData<<0) ;
                    break;
                case 2:
                    lData |= (UINT32)(wData<<16) ;
                    break;
                }
            break;
        case 4:
            if ( reg&0x3 )
                return ERROR ;
            else
                lData = data ;
            break;
        default:
            return ERROR ;
        }
    GT64260_REG_WR(PCI_CFG_DATA, lData);
    return OK ;
    }