sysgt64260intrctl.h

WINDRIVER SBC7410 BSP

/* gt64260IntrCtl.h - Galileo Interrupt Controller definitions */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,20apr02,gtf  modified from sysMpc107Epic.h.
01a,12may01,g_h  created
*/

/*
Description:
Contains structure typedefs for the Galileo interrupt controller.
*/


#ifndef	__INCgt64260IntrCtlh
#define	__INCgt64260IntrCtlh

#ifdef __cplusplus
extern "C" {
#endif

/* includes */

#ifndef	_ASMLANGUAGE

IMPORT STATUS sysGt64260IntrInit(void) ;
IMPORT STATUS sysGt64260MuxedIntEnable(int,int);
	IMPORT STATUS sysGt64260MuxedIntDisable(int,int);

/* structures */
typedef struct intHandlerDesc			/* interrupt handler desciption */
	{
		VOIDFUNCPTR                 vec;	/* interrupt vector */
		int                         arg;	/* interrupt handler argument */
		struct intHandlerDesc *     next;	/* next interrupt handler & argument */
	} INT_HANDLER_DESC;

#define IDMA_INT_TYPE 0
#define TMR_INT_TYPE  1
#define GPP_INT_TYPE  2
		
#define MAIN_INT_CAUSE_L 	(0xc18)  
#define MAIN_INT_CAUSE_H	(0xc68)
#define CPU_INT_MASK_L 		(0xc1c)
#define CPU_INT_MASK_H 		(0xc6c)
#define CPU_SEL_CAUSE 		(0xc70)
#define PCI0_INT_MASK_L 	(0xc24)
#define PCI0_INT_MASK_H 	(0xc64)
#define PCI0_SEL_CAUSE 		(0xc74)
#define PCI1_INT_MASK_L 	(0xca4)
#define PCI1_INT_MASK_H 	(0xce4)
#define PCI1_SEL_CAUSE 		(0xcf4)
#define CPU_INT0_MASK 		(0xe60)
#define CPU_INT1_MASK 		(0xe64)
#define CPU_INT2_MASK 		(0xe68)
#define CPU_INT3_MASK 		(0xe6c)

/* Interrupts will be processed in order of priority */
/* Priority is defined by the priority array which includes ... */
/* 0 reserved */
#define INT_BIT_DEV			0x00000002
#define INT_BIT_DMA			0x00000004
#define INT_BIT_CPU			0x00000008
#define INT_BIT_IDMA0_1		0x00000010
#define INT_BIT_IDMA2_3		0x00000020
#define INT_BIT_IDMA4_5		0x00000040
#define INT_BIT_IDMA6_7		0x00000080
#define INT_BIT_TMR0_1 		0x00000100
#define INT_BIT_TMR2_3 		0x00000200
#define INT_BIT_TMR4_5 		0x00000400
#define INT_BIT_TMR6_7 		0x00000800
#define INT_BIT_PCI0_0 		0x00001000
#define INT_BIT_PCI0_1 		0x00002000
#define INT_BIT_PCI0_2     	0x00004000
#define INT_BIT_PCI0_3     	0x00008000
#define INT_BIT_PCI1_0     	0x00010000
#define INT_BIT_ECC			0x00020000
#define INT_BIT_PCI1_1     	0x00040000
#define INT_BIT_PCI1_2     	0x00080000
#define INT_BIT_PCI1_3     	0x00100000
#define INT_BIT_PCI0_OUTL	0x00200000
#define INT_BIT_PCI0_OUTH	0x00400000
#define INT_BIT_PCI1_OUTL	0x00800000
#define INT_BIT_PCI1_OUTH	0x01000000
/* 25 reserved */
#define INT_BIT_PCI0_INL	0x04000000
#define INT_BIT_PCI0_INH	0x08000000
#define INT_BIT_PCI1_INL	0x10000000
#define INT_BIT_PCI1_INH	0x20000000
/* 30..31 reserved */

/* Main interrupt cause high */
#define INT_BIT_ETH0		0x00000001
#define INT_BIT_ETH1		0x00000002
#define INT_BIT_ETH2		0x00000004
/* 3 reserved */
#define INT_BIT_SDMA		0x00000010
#define INT_BIT_I2C			0x00000020
/* 6 reserved */
#define INT_BIT_BRG			0x00000080
#define INT_BIT_MPSC0		0x00000100
/* 9 reserved */
#define INT_BIT_MPSC1		0x00000400
#define INT_BIT_COMM		0x00000800
/* 12..23 reserved */
#define INT_BIT_GPP7_0		0x01000000
#define INT_BIT_GPP15_8		0x02000000
#define INT_BIT_GPP23_16	0x04000000
#define INT_BIT_GPP31_24	0x08000000
/* 28..31 reserved */ 


/* Main interrupt cause low */
/* interrupt vectors should = int level */
#define INT_VEC_DEV			INT_LVL_DEV
#define INT_VEC_DMA			INT_LVL_DMA
#define INT_VEC_CPU			INT_LVL_CPU
#define INT_VEC_IDMA0_1		INT_LVL_IDMA0_1
#define INT_VEC_IDMA2_3		INT_LVL_IDMA2_3
#define INT_VEC_IDMA4_5		INT_LVL_IDMA4_5
#define INT_VEC_IDMA6_7		INT_LVL_IDMA6_7
#define INT_VEC_TMR0_1 		INT_LVL_TMR0_1
#define INT_VEC_TMR2_3 		INT_LVL_TMR2_3
#define INT_VEC_TMR4_5 		INT_LVL_TMR4_5
#define INT_VEC_TMR6_7 		INT_LVL_TMR6_7
#define INT_VEC_PCI0_0 		INT_LVL_PCI0_0
#define INT_VEC_PCI0_1 		INT_LVL_PCI0_1
#define INT_VEC_PCI0_2     	INT_LVL_PCI0_2
#define INT_VEC_PCI0_3     	INT_LVL_PCI0_3
#define INT_VEC_PCI1_0     	INT_LVL_PCI1_0
#define INT_VEC_ECC			INT_LVL_ECC
#define INT_VEC_PCI1_1     	INT_LVL_PCI1_1
#define INT_VEC_PCI1_2     	INT_LVL_PCI1_2
#define INT_VEC_PCI1_3     	INT_LVL_PCI1_3
#define INT_VEC_PCI0_OUTL	INT_LVL_PCI0_OUTL
#define INT_VEC_PCI0_OUTH	INT_LVL_PCI0_OUTH
#define INT_VEC_PCI1_OUTL	INT_LVL_PCI1_OUTL
#define INT_VEC_PCI1_OUTH	INT_LVL_PCI1_OUTH
#define INT_VEC_PCI0_INL	INT_LVL_PCI0_INL
#define INT_VEC_PCI0_INH	INT_LVL_PCI0_INH
#define INT_VEC_PCI1_INL	INT_LVL_PCI1_INL
#define INT_VEC_PCI1_INH	INT_LVL_PCI1_INH
#define INT_VEC_ETH0		INT_LVL_ETH0
#define INT_VEC_ETH1		INT_LVL_ETH1
#define INT_VEC_ETH2		INT_LVL_ETH2
#define INT_VEC_SDMA		INT_LVL_SDMA
#define INT_VEC_I2C			INT_LVL_I2C
#define INT_VEC_BRG			INT_LVL_BRG
#define INT_VEC_MPSC0		INT_LVL_MPSC0
#define INT_VEC_MPSC1		INT_LVL_MPSC1
#define INT_VEC_COMM		INT_LVL_COMM
#define INT_VEC_GPP7_0		INT_LVL_GPP7_0
#define INT_VEC_GPP15_8		INT_LVL_GPP15_8
#define INT_VEC_GPP23_16	INT_LVL_GPP23_16
#define INT_VEC_GPP31_24	INT_LVL_GPP31_24


/* NOTE: priorities must be incremented and be a continuous range
   of integers starting from 0. The relative priorities can be
   rearranged as desired. */

#define INT_PRI_LOW			0
#define INT_PRI_DEV			0
#define INT_PRI_DMA			1
#define INT_PRI_CPU			2
#define INT_PRI_IDMA0_1		3
#define INT_PRI_IDMA2_3		4
#define INT_PRI_IDMA4_5		5
#define INT_PRI_IDMA6_7		6
#define INT_PRI_TMR0_1		7
#define INT_PRI_TMR2_3		8 
#define INT_PRI_TMR4_5		9 
#define INT_PRI_TMR6_7		10
#define INT_PRI_PCI0_0		11
#define INT_PRI_PCI0_1		12
#define INT_PRI_PCI0_2		13
#define INT_PRI_PCI0_3		14
#define INT_PRI_PCI1_0		15
#define INT_PRI_ECC			16
#define INT_PRI_PCI1_1  	17
#define INT_PRI_PCI1_2 		18
#define INT_PRI_PCI1_3 		19
#define INT_PRI_PCI0_OUTL	20
#define INT_PRI_PCI0_OUTH	21
#define INT_PRI_PCI1_OUTL	22
#define INT_PRI_PCI1_OUTH	23
#define INT_PRI_PCI0_INL	24
#define INT_PRI_PCI0_INH	25
#define INT_PRI_PCI1_INL	26
#define INT_PRI_PCI1_INH	27
#define INT_PRI_ETH0		28
#define INT_PRI_ETH1		29
#define INT_PRI_ETH2		30
#define INT_PRI_SDMA		31
#define INT_PRI_I2C			32
#define INT_PRI_BRG			33
#define INT_PRI_MPSC0		34
#define INT_PRI_MPSC1		35
#define INT_PRI_COMM		36
#define INT_PRI_GPP7_0		37
#define INT_PRI_GPP15_8		38
#define INT_PRI_GPP23_16 	39
#define INT_PRI_GPP31_24	40
#define INT_PRI_HIGH		INT_PRI_GPP31_24

#define INT_LVL_LOW			INT_PRI_LOW
#define INT_LVL_DEV			INT_PRI_DEV
#define INT_LVL_DMA			INT_PRI_DMA
#define INT_LVL_CPU			INT_PRI_CPU
#define INT_LVL_IDMA0_1		INT_PRI_IDMA0_1
#define INT_LVL_IDMA2_3		INT_PRI_IDMA2_3
#define INT_LVL_IDMA4_5		INT_PRI_IDMA4_5
#define INT_LVL_IDMA6_7		INT_PRI_IDMA6_7
#define INT_LVL_TMR0_1		INT_PRI_TMR0_1
#define INT_LVL_TMR2_3		INT_PRI_TMR2_3
#define INT_LVL_TMR4_5		INT_PRI_TMR4_5
#define INT_LVL_TMR6_7		INT_PRI_TMR6_7
#define INT_LVL_PCI0_0		INT_PRI_PCI0_0
#define INT_LVL_PCI0_1		INT_PRI_PCI0_1
#define INT_LVL_PCI0_2		INT_PRI_PCI0_2
#define INT_LVL_PCI0_3		INT_PRI_PCI0_3
#define INT_LVL_PCI1_0		INT_PRI_PCI1_0
#define INT_LVL_ECC			INT_PRI_ECC
#define INT_LVL_PCI1_1		INT_PRI_PCI1_1
#define INT_LVL_PCI1_2 		INT_PRI_PCI1_2
#define INT_LVL_PCI1_3 		INT_PRI_PCI1_3
#define INT_LVL_PCI0_OUTL	INT_PRI_PCI0_OUTL
#define INT_LVL_PCI0_OUTH	INT_PRI_PCI0_OUTH
#define INT_LVL_PCI1_OUTL	INT_PRI_PCI1_OUTL
#define INT_LVL_PCI1_OUTH	INT_PRI_PCI1_OUTH
#define INT_LVL_PCI0_INL	INT_PRI_PCI0_INL
#define INT_LVL_PCI0_INH	INT_PRI_PCI0_INH
#define INT_LVL_PCI1_INL	INT_PRI_PCI1_INL
#define INT_LVL_PCI1_INH	INT_PRI_PCI1_INH
#define INT_LVL_ETH0		INT_PRI_ETH0
#define INT_LVL_ETH1		INT_PRI_ETH1
#define INT_LVL_ETH2		INT_PRI_ETH2
#define INT_LVL_SDMA		INT_PRI_SDMA
#define INT_LVL_I2C			INT_PRI_I2C
#define INT_LVL_BRG			INT_PRI_BRG
#define INT_LVL_MPSC0		INT_PRI_MPSC0
#define INT_LVL_MPSC1		INT_PRI_MPSC1
#define INT_LVL_COMM		INT_PRI_COMM
#define INT_LVL_GPP7_0		INT_PRI_GPP7_0
#define INT_LVL_GPP15_8		INT_PRI_GPP15_8
#define INT_LVL_GPP23_16	INT_PRI_GPP23_16
#define INT_LVL_GPP31_24	INT_PRI_GPP31_24
#define INT_LVL_HIGH		INT_PRI_HIGH

#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif	/* __INCgt64260IntrCtlh */