rominit.s

WINDRIVER SBC7410 BSP

	/* Turn on FP */
	xor	r3, r3, r3
	sync
	ori     r3, r3, _PPC_MSR_FP
	sync
	mtmsr   r3
	isync

	/* Init the floating point control/status register */
	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync
	
	/* Initialize the floating point data registers to a known state */
	mfspr   r3,8
	lfs     f0,0(r3)
	lfs     f1,0(r3)
	lfs     f2,0(r3)
	lfs     f3,0(r3)
	lfs     f4,0(r3)
	lfs     f5,0(r3)
	lfs     f6,0(r3)
	lfs     f7,0(r3)
	lfs     f8,0(r3)
	lfs     f9,0(r3)
	lfs     f10,0(r3)
	lfs     f11,0(r3)
	lfs     f12,0(r3)
	lfs     f13,0(r3)
	lfs     f14,0(r3)
	lfs     f15,0(r3)
	lfs     f16,0(r3)
	lfs     f17,0(r3)
	lfs     f18,0(r3)
	lfs     f19,0(r3)
	lfs     f20,0(r3)
	lfs     f21,0(r3)
	lfs     f22,0(r3)
	lfs     f23,0(r3)
	lfs     f24,0(r3)
	lfs     f25,0(r3)
	lfs     f26,0(r3)
	lfs     f27,0(r3)
	lfs     f28,0(r3)
	lfs     f29,0(r3)
	lfs     f30,0(r3)
	lfs     f31,0(r3)
	sync
	
	/*   Turn off FP (by clearing MSR) */
	xor	r4,r4,r4
	isync  
	mtmsr   r4
	isync  

	/* Init the Segment registers */
	xor	r3, r3, r3
	isync
	mtsr    0,r3
	mtsr    1,r3
	mtsr    2,r3
	mtsr    3,r3
	mtsr    4,r3
	mtsr    5,r3
	mtsr    6,r3
	mtsr    7,r3
	mtsr    8,r3
	mtsr    9,r3
	mtsr    10,r3
	mtsr    11,r3
	mtsr    12,r3
	mtsr    13,r3
	mtsr    14,r3
	mtsr    15,r3
	isync

        /* Turn off data and instruction cache enable bits */
	xor	r4,r4,r4
	ori     r4, r4, (_PPC_HID0_DCE | _PPC_HID0_ICE)
	mfspr   r3, HID0
	andc    r3,r3,r4
	sync
	mtspr   HID0, r3
	isync

        /* Turn on FP, machine check ME, and recoverable interrupt RI */
	xor 	r4,r4,r4
	ori	r4,r4,(_PPC_MSR_FP | _PPC_MSR_ME | _PPC_MSR_RI)
	sync
	mtmsr   r4
	isync 

	/* fake a Decrementer Exception Handler (i.e. rfi @ 0x900) */
	xor 	r0,r0,r0		/* clear r0 */
	lis 	r3,HI(0x4C000064)
	ori	r3,r3,LO(0x4C000064)	/* load rfi (0x4c000064) to */
	stw 	r3,0x900(r0)		/* store rfi at 0x00000900 */

	bl	romClearBATs
	
        /* invalidate the MPU's data/instruction caches */
	
	mfspr	r4,HID0
	mr	r3,r4
	/* for manual clearing of xCFI bits */
	ori     r3, r3, (_PPC_HID0_ICFI | _PPC_HID0_DCFI)
	sync
	mtspr   HID0, r3
	mtspr   HID0, r4
	isync
       
	bl	romInvalidateTLBs
	bl	romMinimumBATsInit
	
	 /* set SDR1 to 0 */
	 xor	r3,r3,r3
	 mtspr   SDR1,r3
	 isync

	 /* Turn on Data Relocation */
	 sync
	 mfmsr   r3
  	 ori     r3, r3, _PPC_MSR_DR
	 isync
	 mtmsr   r3
	 isync
 
#if FALSE /* ZZZZZZZZZZZZZZ */
/* NOTE: this works with the GT64260 but does not work with the GT64260A */

	/* turn the Instruction cache ON for faster FLASH ROM boots */
	/* somewhere later this is turned off... */
	mfspr	r3,HID0
	ori	r3,r3,0x8000
	isync
	mtspr	HID0,r3
	isync
#endif

	/* TODO - setup other necessary controllers */

#if	FALSE	/* EABI SDA not supported yet */

    /* initialize r2 and r13 according to EABI standard */
	lis     r2, HI(_SDA2_BASE_)
	ori	r2, r2, LO(_SDA2_BASE_)
	lis     r13, HI(_SDA_BASE_)
	ori	r13, r13, LO(_SDA_BASE_)
#endif

	/* initialize the stack pointer */
	lis     sp, HI(STACK_ADRS)			/* NOTE:  sp = r1 */
	ori     sp, sp, LO(STACK_ADRS)

	sync
	isync

	/* go to C entry point */
        or	r3, r11, r11                    /* restore start type */
        
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

	lis     r6, HI(romStart)
	ori	r6, r6, LO(romStart)

	lis     r7, HI(romInit)
	ori	r7, r7, LO(romInit)

	lis     r8, HI(ROM_TEXT_ADRS)
	ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 
	mtlr	r6

	lis	r4,0
	ori	r4,r4,0x9000
	lis	r5,0xdead
	stw	r5,0x0(r4)

	blr

	.long 0x12345678		/* DEBUG */
FUNC_END(romInit)
FUNC_END(_romInit)


/***************************************************************************
*
* romClearBATs - clearing all the BAT's register.
*
* This routine will zero the BAT's register.
*
* SYNOPSIS
* \ss
* void romClearBATs
*     (
*     void
*     )
* \se
*
* SEE ALSO: romInvalidateTLBs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romClearBATs)
        /* zero out the BAT registers */
	xor	r3,r3,r3
	isync
	mtspr	IBAT0U,r3	/* clear all upper BATS first */
	mtspr	IBAT1U,r3
	mtspr	IBAT2U,r3
	mtspr	IBAT3U,r3
	mtspr	DBAT0U,r3
	mtspr	DBAT1U,r3
	mtspr	DBAT2U,r3
	mtspr	DBAT3U,r3

	mtspr	IBAT0L,r3	/* then clear lower BATS */
	mtspr	IBAT1L,r3
	mtspr	IBAT2L,r3
	mtspr	IBAT3L,r3
	mtspr	DBAT0L,r3
	mtspr	DBAT1L,r3
	mtspr	DBAT2L,r3
	mtspr	DBAT3L,r3
	isync

	mfspr	r3,PVR		/* read PVR */
	srwi	r3,r3,12
	andi.	r3,r3,0xff
	cmpwi	r3,0x83
	beq	romIs7x5
	blr
romIs7x5:
	xor	r3,r3,r3

	mtspr	IBAT4U,r3
	mtspr	IBAT5U,r3
	mtspr	IBAT6U,r3
	mtspr	IBAT7U,r3               

	mtspr	DBAT4U,r3
	mtspr	DBAT5U,r3
	mtspr	DBAT6U,r3
	mtspr	DBAT7U,r3

	mtspr	IBAT4L,r3
	mtspr	IBAT5L,r3
	mtspr	IBAT6L,r3
	mtspr	IBAT7L,r3

	mtspr	DBAT4L,r3
	mtspr	DBAT5L,r3
	mtspr	DBAT6L,r3
	mtspr	DBAT7L,r3

	isync

	blr
FUNC_END(romClearBATs)

/***************************************************************************
*
* romInvalidateTLBs - invalidate the TLB's.
*
* This routine will invalidate the TLB's.
*
* SYNOPSIS
* \ss
* void romInvalidateTLBs
*     (
*     void
*     )
* \se
*
* SEE ALSO: romClearBATs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInvalidateTLBs)
        /* invalidate entries within both TLBs */
	li	r3,128
	xor	r4,r4,r4	/* r4 = 0    */
	mtctr	r3		/* CTR = 32  */
	isync			/* context sync req'd before tlbie */
tlbloop:
	tlbie	r4
	addi	r4,r4,0x1000	/* increment bits 15-19 */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */
	sync			/* sync instr req'd after tlbie      */

	isync			/* context sync req'd before tlbie */
	
	blr
FUNC_END(romInvalidateTLBs)

/***************************************************************************
*
* romMinimumBATsInit - initialize the minimum BAT's
*
* This routine will initialize the minimum BAT's register, and turn MMU on.
*
* SYNOPSIS
* \ss
* void romMinimumBATsInit
*     (
*     void
*     )
* \se
*
* NOTE: When the MMU is disabled, the processor is said to be in Real Addressing 
*       Mode. In this mode, all memory accesses are governed by a default set of 
*       bit values for the WIMG attribute bits. For data accesses, the default 
*       WIMG = 0011 and for instruction fetches default WIMG=0001. In both cases, 
*       the guarded (G) bit is set and the cache-inhibit (I) bit is clear. In 
*       other words, in real addressing mode, the entire address space of the 
*       processor is cacheable ("NOT cache-inhibited") and guarded -- independent 
*       of whether the caches are enabled or not.
*
*       The guarded attribute merely prevents out-of-order and speculative 
*       *loads*. More details are avalible in section 5.2.1.5 of the PowerPC 
*       programming environments manual for a more complete explanation of the 
*       guarded attribute. While guarded is a necessary condition for those 
*       memory spaces in which devices reside, it is not a sufficient condition. 
*       Memory accesses to devices must be both guarded and cache inhibited. 
*       Physically disabling the data cache does not provide this second, 
*       equally necessary, condition.
*
*       Above, I used the term "NOT cache-inhibited" to draw attention to an 
*       important distinction between cache-inhibited memory accesses and 
*       cacheable memory accesses that are made while the cache itself is 
*       disabled. A naive interpretation of "cacheability" holds that these two 
*       concepts are equivalent -- they are not. To prevent out-of-order 
*       *stores* to devices, we must mark the memory addresses at which those 
*       devices reside as cache inhibited. The only way to do this is to enable 
*       the MMU. So it holds that in order to enforce in-order loads AND stores, 
*       we must enable the MMU and mark the appropriate memory regions as CI & G.
*
* SEE ALSO: romClearBATs(), romInvalidateTLBs()

* RETURNS: N/A
*/

FUNC_BEGIN(romMinimumBATsInit)
	LOADPTR(r3,DBAT0L_VALUE)
	sync
	mtspr	DBAT0L,r3		
	isync

	LOADPTR(r3,DBAT0U_VALUE)
	sync
	mtspr	DBAT0U,r3		
	isync

	LOADPTR(r3,DBAT1L_VALUE)
	sync
	mtspr	DBAT1L,r3		
	isync

	LOADPTR(r3,DBAT1U_VALUE)
	sync				/* (PCI register space)     */
	mtspr	DBAT1U,r3		
	isync

	LOADPTR(r3,DBAT2L_VALUE)
	sync
	mtspr	DBAT2L,r3		
	isync

	LOADPTR(r3,DBAT2U_VALUE)
	sync
	mtspr	DBAT2U,r3		
	isync

	LOADPTR(r3,DBAT3L_VALUE)
	isync
	mtspr	DBAT3L,r3
	isync

	LOADPTR(r3,DBAT3U_VALUE)
	isync
	mtspr	DBAT3U,r3
	isync
	
	blr
	
FUNC_END(romMinimumBATsInit)