rominit.s

WINDRIVER SBC7410 BSP

/* romInit.s - Wind River wrSbc7410 ROM initialization module */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,19apr02,gtf  Modified for sbc7410 bsp.
01d,20dec01,kab  Fix for diab
01c,23oct01,g_h  Cleaning for T2.2
01d,21may01,kab  .ascii directives fail to compile
01c,08dec98,est	 ported from yk603 to est603
*/

/*

DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

RomInit() typically masks interrupts in the processor, sets the initial
stack pointer (to STACK_ADRS which is defined in configAll.h), and
readies system memory by configuring the DRAM controller if necessary.
Other hardware and device initialization is performed later in the
BSP's sysHwInit() routine.

A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().

WARNING:
This code must be Position Independent Code (PIC).  This means that it
should not contain any absolute address references.  If an absolute address
must be used, it must be relocated by the macro ROM_ADRS(x).  This macro
will convert the absolute reference to the appropriate address within
ROM space no matter how the boot code was linked. (For PPC, ROM_ADRS does
not work.  You must subtract _romInit and add ROM_TEXT_ADRS to each
absolute address). (NOTE: ROM_ADRS(x) macro does not work for current
PPC compiler).

This code should not call out to subroutines declared in other modules,
specifically sysLib.o, and sysALib.o.  If an outside module is absolutely
necessary, it can be linked into the system by adding the module 
to the makefile variable BOOT_EXTRA.  If the same module is referenced by
other BSP code, then that module must be added to MACH_EXTRA as well.
Note that some C compilers can generate code with absolute addresses.
Such code should not be called from this module.  If absolute addresses
cannot be avoided, then only ROM resident code can be generated from this
module.  Compressed and uncompressed bootroms or VxWorks images will not
work if absolute addresses are not processed by the macro ROM_ADRS.

WARNING:
The most common mistake in BSP development is to attempt to do too much
in romInit.s.  This is not the main hardware initialization routine.
Only do enough device initialization to get memory functioning.  All other
device setup should be done in sysLib.c, as part of sysHwInit().

Unlike other RTOS systems, VxWorks does not use a single linear device
initialization phase.  It is common for inexperienced BSP writers to take
a BSP from another RTOS, extract the assembly language hardware setup
code and try to paste it into this file.  Because VxWorks provides 3
different memory configurations, compressed, uncompressed, and rom-resident,
this strategy will usually not work successfully.

WARNING:
The second most common mistake made by BSP writers is to assume that
hardware or CPU setup functions done by romInit.o do not need to be
repeated in sysALib.s or sysLib.c.  A vxWorks image needs only the following
from a boot program: The startType code, and the boot parameters string
in memory.  Each VxWorks image will completely reset the CPU and all
hardware upon startup.  The image should not rely on the boot program to
initialize any part of the system (it may assume that the memory controller
is initialized).

This means that all initialization done by romInit.s must be repeated in
either sysALib.s or sysLib.c.  The only exception here could be the
memory controller.  However, in most cases even that can be
reinitialized without harm.

Failure to follow this rule may require users to rebuild bootrom's for
minor changes in configuration.  It is WRS policy that bootroms and vxWorks
images should not be linked in this manner.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "gt64260Def.h"	
#include "wrSbc7410.h"


        /* globals */

	FUNC_EXPORT(_romInit)     /* start of system code */
	FUNC_EXPORT(romInit)      /* start of system code */
	FUNC_EXPORT(_romInitWarm) /* start of system code */
	FUNC_EXPORT(romInitWarm)  /* start of system code */

        /* externals */
	FUNC_IMPORT(romStart)     /* system initialization routine */

        _WRS_TEXT_SEG_START

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

	/* This is the cold boot entry (ROM_TEXT_ADRS) */
	bl	cold
        nop                     /* byte align to an 8 byte boundary */
	bl	_warmstart

	/* copyright notice appears at beginning of ROM (in TEXT segment) */
	.ascii   "Copyright 1984-2002 Wind River Systems, Inc."
	.align 2

cold:
	xor     r4,r4,r4
	isync
	mtmsr   r4
	isync
	
	LOADPTR(r4, GT64260_BASE_ADRS)

	/*
	; SCS0  SDRAM SODIDD
	; range 0 to 0x0FFFFFFFF
	;	
	*/
	LOADPTR(r3,SCS0LADDR_VALUE)
	LOADPTR(r5,SCS0LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SCS0HADDR_VALUE)
	LOADPTR(r5,SCS0HADDR)
	stwbrx	r3,r5,r4

	/*
	; SCS1  not used
	*/
	LOADPTR(r3,SCS1LADDR_VALUE)
	LOADPTR(r5,SCS1LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SCS1HADDR_VALUE)
	LOADPTR(r5,SCS1HADDR)
	stwbrx	r3,r5,r4

	/*
	; SCS2  not used
	*/
	LOADPTR(r3,SCS2LADDR_VALUE)
	LOADPTR(r5,SCS2LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SCS2HADDR_VALUE)
	LOADPTR(r5,SCS2HADDR)
	stwbrx	r3,r5,r4

	/*
	; SCS3  not used
	*/
	LOADPTR(r3,SCS3LADDR_VALUE)
	LOADPTR(r5,SCS3LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SCS3HADDR_VALUE)
	LOADPTR(r5,SCS3HADDR)
	stwbrx	r3,r5,r4

	/*
	; CS0 EEPROM, LEDs and GP
	; address size  = 8 MB
	; address range = 0x1C000000
	*/
	LOADPTR(r3,CS0LADDR_VALUE)
	LOADPTR(r5,CS0LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,CS0HADDR_VALUE)
	LOADPTR(r5,CS0HADDR)
	stwbrx	r3,r5,r4

	/*
	; CS1 Mailbox
	; address size  = 8 MB
	; address range = 0x1C800000
	*/
	LOADPTR(r3,CS1LADDR_VALUE)
	LOADPTR(r5,CS1LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,CS1HADDR_VALUE)
	LOADPTR(r5,CS1HADDR)
	stwbrx	r3,r5,r4

	/*
	; CS2 UART
	; address size  = 16 MB
 	; address range = 0x1D000000
	*/
	LOADPTR(r3,CS2LADDR_VALUE)
	LOADPTR(r5,CS2LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,CS2HADDR_VALUE)
	LOADPTR(r5,CS2HADDR)
	stwbrx	r3,r5,r4

	/*
	; CS3 CPIO
	; address size  = 8 MB
	; address range = 0x1E000000
	*/
	LOADPTR(r3,CS3LADDR_VALUE)
	LOADPTR(r5,CS3LADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,CS3HADDR_VALUE)
	LOADPTR(r5,CS3HADDR)
	stwbrx	r3,r5,r4

	/*
	; BOOTCS FLASH
	; address size  = 16 MB
	; address range = 0xFF000000
	*/
	LOADPTR(r3,BOOTLADDR_VALUE)
	LOADPTR(r5,BOOTLADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,BOOTHADDR_VALUE)
	LOADPTR(r5,BOOTHADDR)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_CFG_VALUE)
	LOADPTR(r5,SD_CFG)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_MODE0_VALUE)
	LOADPTR(r5,SD_MODE)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ACTRL_VALUE)
	LOADPTR(r5,SD_ACTRL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_TIM_VALUE)
	LOADPTR(r5,SD_TIM)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_UCTRL_VALUE)
	LOADPTR(r5,SD_UCTRL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ICCL_VALUE)
	LOADPTR(r5,SD_ICCL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ICCH_VALUE)
	LOADPTR(r5,SD_ICCH)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_BANK0_VALUE)
	LOADPTR(r5,SD_BANK0)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_BANK1_VALUE)
	LOADPTR(r5,SD_BANK1)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_BANK2_VALUE)
	LOADPTR(r5,SD_BANK2)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_BANK3_VALUE)
	LOADPTR(r5,SD_BANK3)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ERRDL_VALUE)
	LOADPTR(r5,SD_ERRDL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ERRDL_VALUE)
	LOADPTR(r5,SD_ERRDL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ERRAD_VALUE)
	LOADPTR(r5,SD_ERRAD)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_RECC_VALUE)
	LOADPTR(r5,SD_RECC)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_CECC_VALUE)
	LOADPTR(r5,SD_CECC)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ECCCTRL_VALUE)
	LOADPTR(r5,SD_ECCCTRL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,SD_ECCEC_VALUE)
	LOADPTR(r5,SD_ECCEC)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_BANK0_VALUE)
	LOADPTR(r5,DEV_BANK0)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_BANK1_VALUE)
	LOADPTR(r5,DEV_BANK1)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_BANK2_VALUE)
	LOADPTR(r5,DEV_BANK2)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_BANK3_VALUE)
	LOADPTR(r5,DEV_BANK3)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_BOOT_VALUE)
	LOADPTR(r5,DEV_BOOT)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_CONTROL_VALUE)
	LOADPTR(r5,DEV_CONTROL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_ICCL_VALUE)
	LOADPTR(r5,DEV_ICCL)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_ICCH_VALUE)
	LOADPTR(r5,DEV_ICCH)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_INTC_VALUE)
	LOADPTR(r5,DEV_INTC)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_INTM_VALUE)
	LOADPTR(r5,DEV_INTM)
	stwbrx	r3,r5,r4

	LOADPTR(r3,DEV_EADDR_VALUE)
	LOADPTR(r5,DEV_EADDR)
	stwbrx	r3,r5,r4
	
	li	r11, BOOT_COLD
	bl	start	/* skip over next instruction */

	.long 0x12345678 /* DEBUG */
			
_warmstart:
	xor     r4,r4,r4
	isync
	mtmsr   r4
	isync

	/* disable L2 cache */
	mtspr 	1017,4
	isync

	/* disable private memory control register */
	mtspr   1016,4
	isync

	or	r11, r3, r3	/* startType to r11 */

start:
	/* Zero-out registers: r0 & SPRGs */
	xor     r0,r0,r0
	isync
	mtspr   SPRG0,r0
	mtspr   SPRG1,r0
	mtspr   SPRG2,r0
	mtspr   SPRG3,r0