wrsbc7410.h

WINDRIVER SBC7410 BSP

#define CPU_TYPE_7400  		  0xC0 /* PPC 7400 Altivec */
#define CPU_TYPE_7410  		  0xC1 /* PPC 7410 Altivec */

/* MPC74xx (Max) Support */

/* Max SPRs */

#define VRSAVE                    256  /* VMX Save register */
#define UBAMR                     935  /* Performance monitor mask */
#define UMMCR2                    928  /* Performance monitor control */
#define BAMR                      951  /* Performance monitor mask */
#define MMCR2                     944  /* Performance monitor control */
#define MSSCR0                    1014 /* Memory Subsystem control */
#define MSSCR1                    1015 /* Memory Subsystem debug */
#define PIR                       1023 /* Processor ID register */

/* Max HID0 bit definitions */

#define _PPC_HID0_NOPDST          0x2	/* Nop dst, dstt, dstst, &dststt*/
#define _PPC_HID0_NOPTI           0x1	/* Nop dcbt and dbtst */

/* AltiVec Exceptions */

#define _EXC_VMX_UNAVAIL          0x0f20 /* VMX Unavailable Exception */
#define _EXC_VMX_ASSIST           0x1600 /* VMX Assist Exception */
#define SIZEOF_EXCEPTION          0x0030 /* VxWorks Exc is 48 bytes Max*/

/* Extra 4 IBAT register for the MPC755 */

#define IBAT4U		          560 /* instruction BAT register */
#define IBAT4L		          561 /* instruction BAT register */
#define IBAT5U		          562 /* instruction BAT register */
#define IBAT5L		          563 /* instruction BAT register */
#define IBAT6U		          564 /* instruction BAT register */
#define IBAT6L		          565 /* instruction BAT register */
#define IBAT7U		          566 /* instruction BAT register */
#define IBAT7L		          567 /* instruction BAT register */

/* Extra 4 DBAT register for the MPC755 */

#define DBAT4U		          568 /* data BAT register */
#define DBAT4L		          569 /* data BAT register */
#define DBAT5U		          570 /* data BAT register */
#define DBAT5L		          571 /* data BAT register */
#define DBAT6U		          572 /* data BAT register */
#define DBAT6L		          573 /* data BAT register */
#define DBAT7U		          574 /* data BAT register */
#define DBAT7L		          575 /* data BAT register */

#ifndef _MMU_UBAT_BL_512M
#define _MMU_UBAT_BL_512M       0x00003ffc      /* block size 512M          */
#endif  _MMU_UBAT_BL_512M

/* General */

#ifndef WRS_ASM
#define WRS_ASM(x)                __asm__ volatile (x)
#endif

#undef  EIEIO_SYNC
#define EIEIO_SYNC                WRS_ASM (" eieio; sync")

#undef  EIEIO
#define EIEIO                     WRS_ASM (" eieio")

#define REG_8BIT  1
#define REG_16BIT 2
#define REG_32BIT 4

#define NV_RAM_WR_ENBL			  sysNvRamWrEnbl()
#define NV_RAM_WR_DSBL			  sysNvRamWrDsbl()
#define NV_RAM_READ				  sysNvRamRead
#define NV_RAM_WRITE			  sysNvRamWrite
#ifndef _ASMLANGUAGE
void sysNvRamWrEnbl(void);
void sysNvRamWrDsbl(void);
void sysNvRamWrite(int offset, UINT8 data);
UINT8 sysNvRamRead(int offset);

UINT32 sysPciInLong(UINT32);
void sysPciOutLong(UINT32, UINT32);
#endif

#define FEI_PCI_VENDOR_ID   	0x8086  /* Intel PCI vendor ID */
#define FEI_PCI_DEVICE_ID   	0x1030  /* Intel FEI PCI device ID */
#define FEI_IDSEL		0x7	/* device number 7 -> AD17 -> PCI-1 */

#define GEI_PCI_VENDOR_ID	0x8086	/* Intel PCI vendor ID */
#define GEI_PCI_DEVICE_ID	0x1001	/* Intel GEI PCI device ID */
#define GEI_IDSEL		0x7	/* device number 7 -> AD17 -> PCI-1 */

#if defined(INCLUDE_PCI_STANDALONE)
  #define PCI_IO_GEIFEI_ADRS		0x20000000      /* default I/O space start */
  #define PCI_MEM_GEIFEI_ADRS		0x22000000	    /* default mem space start */
  #define GEIFEI_INT_VEC		INT_VEC_GPP15_8 /* GPP pin 9 */
  #define GEIFEI_INT_LVL		INT_LVL_GPP15_8
#else 
  #define PCI_IO_GEIFEI_ADRS		0x10000000      /* default I/O space start */
  #define PCI_MEM_GEIFEI_ADRS		0x12000000	    /* default mem space start */
  #define GEIFEI_INT_VEC		INT_VEC_GPP7_0 /* GPP pin 5 */
  #define GEIFEI_INT_LVL		INT_LVL_GPP7_0
#endif  /* INCLUDE_PCI_STANDALONE */

#define INTEL_21154_PCI_VENDOR_ID	0x1011
#define INTEL_21154_PCI_DEVICE_ID	0x0026

#define GT64260_PCI0_IDSEL		0x6		/* device number 6 -> AD16 -> PCI-0 */
#define GT64260_PCI1_IDSEL		0x6		/* device number 6 -> AD16 -> PCI-0 */
#define INTEL_21554_PRI_IDSEL	0x7			/* device number 7 -> AD17 -> PCI-0 */

#define GSYNC_PRE nop;nop;isync;eieio;isync;
#define GSYNC_POST nop;nop;isync;eieio;isync;nop;nop;

/* Constants used in romInit.s */
/* CPU */

#define SCS0LADDR 	0x008
#define SCS0HADDR       0x010 
#define SCS1LADDR       0x208
#define SCS1HADDR       0x210
#define SCS2LADDR       0x018  
#define SCS2HADDR       0x020 
#define SCS3LADDR       0x218
#define SCS3HADDR       0x220
#define CS0LADDR        0x028
#define CS0HADDR        0x030
#define CS1LADDR        0x228
#define CS1HADDR        0x230
#define CS2LADDR        0x248
#define CS2HADDR        0x250
#define CS3LADDR        0x038
#define CS3HADDR        0x040
#define BOOTLADDR       0x238
#define BOOTHADDR       0x240


#define SCS0LADDR_VALUE 0x00000000
#define SCS0HADDR_VALUE 0x000000ff 
#define SCS1LADDR_VALUE 0x00000008
#define SCS1HADDR_VALUE 0x00000000
#define SCS2LADDR_VALUE 0x00000008
#define SCS2HADDR_VALUE 0x00000000 
#define SCS3LADDR_VALUE 0x00000008
#define SCS3HADDR_VALUE 0x00000000 
#define CS0LADDR_VALUE  0x000001c0 
#define CS0HADDR_VALUE  0x000001c7
#define CS1LADDR_VALUE  0x000001c8
#define CS1HADDR_VALUE  0x000001cf
#define CS2LADDR_VALUE  0x000001d0
#define CS2HADDR_VALUE  0x000001df
#define CS3LADDR_VALUE  0x000001e0
#define CS3HADDR_VALUE  0x000001e7
#define BOOTLADDR_VALUE 0x00000ff0
#define BOOTHADDR_VALUE 0x00000fff


/* SDRAM */

#define SD_CFG		0x448
#define SD_MODE 	0x474
#define SD_ACTRL	0x47c
#define SD_TIM		0x4b4
#define SD_UCTRL	0x4a4
#define SD_ICCL		0x4a8
#define SD_ICCH		0x4ac
#define SD_ICCTO	0x4b0
#define SD_BANK0	0x44c
#define SD_BANK1	0x450
#define SD_BANK2	0x454
#define SD_BANK3	0x458
#define SD_ERRDL    0x484  
#define SD_ERRDH    0x480 
#define SD_ERRAD    0x490
#define SD_RECC     0x488
#define SD_CECC     0x48C
#define SD_ECCCTRL  0x494
#define SD_ECCEC    0x498

#define SD_CFG_VALUE        0xd8e1c200
#define SD_TIM_VALUE        0x0000052a 
#define SD_UCTRL_VALUE      0x00000100 
#define SD_ICCL_VALUE       0x00765432
#define SD_ICCH_VALUE       0x00765432
#define SD_BANK0_VALUE      0x0000c000 
#define SD_BANK1_VALUE      0x0000c000 
#define SD_BANK2_VALUE      0x0000c000 
#define SD_BANK3_VALUE      0x0000c000 
#define SD_ERRDL_VALUE      0x00000000 
#define SD_ERRDH_VALUE      0x00000000 
#define SD_ERRAD_VALUE      0x00000000 
#define SD_RECC_VALUE       0x00000000 
#define SD_CECC_VALUE       0x00000000 
#define SD_ECCCTRL_VALUE    0x00000000 
#define SD_ECCEC_VALUE      0x00000000 
#define SD_ACTRL_VALUE      0x0000000a 
#define SD_MODE3_VALUE   	0x03000000 
#define SD_MODE0_VALUE   	0x00000000 


/* device */    
#define DEV_BANK0    0x45C
#define DEV_BANK1    0x460
#define DEV_BANK2    0x464
#define DEV_BANK3    0x468
#define DEV_BOOT     0x46C
#define DEV_CONTROL  0x4C0
#define DEV_ICCL     0x4C8
#define DEV_ICCH     0x4CC
#define DEV_INTC     0x4D0
#define DEV_INTM     0x4D4
#define DEV_EADDR	 0x4D8

#define DEV_BANK0_VALUE   0xffcfffff 
#define DEV_BANK1_VALUE   0xffcfffff
#define DEV_BANK2_VALUE   0xf00fffff
#define DEV_BANK3_VALUE   0xffefffff
#define DEV_BOOT_VALUE    0xf02fffff
#define DEV_CONTROL_VALUE 0x0003ffff
#define DEV_ICCL_VALUE    0x11765432
#define DEV_ICCH_VALUE    0x11765432
#define DEV_INTC_VALUE    0x00000000
#define DEV_INTM_VALUE    0x00000000
#define DEV_EADDR_VALUE   0x00000000


/* BAT init values */

#define DBAT0L_VALUE	0x00000032
#define DBAT0U_VALUE	0x00001fff

#define DBAT1L_VALUE	0xf000003a
#define DBAT1U_VALUE	0xf0001fff

#define DBAT2L_VALUE	0x1000003a  /* PCI-0 space; PCI_0 MEM0-MEM3, PCI_0 I/O */
#define DBAT2U_VALUE	0x10001fff

#define DBAT3L_VALUE	0x2000003a 	/* PCI-1 space; PCI_1 MEM0-MEM3, PCI_1 I/O */
#define DBAT3U_VALUE	0x20001fff

#define VM_STATE_MASK_FOR_ALL \
            VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |VM_STATE_MASK_CACHEABLE
#define VM_STATE_FOR_IO \
            VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
#define VM_STATE_FOR_MEM_OS \
            VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#define VM_STATE_FOR_MEM_APPLICATION \
            VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#define VM_STATE_FOR_PCI \
            VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT

#endif	/* __INCwrSbc7410h */