wrsbc7410.h

WINDRIVER SBC7410 BSP

/* wrSbc7410.h - board header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,06jan03,dee  cleanup for GEI/FEI devices
01e,19apr02,gtf  Modified from wrPpmc74xx.h
01d,04feb02,g_h  Move L2 cache macros to sysCache.h
01c,23oct01,g_h  Cleaning for T2.2
01b,16sep01,dat  Use of WRS_ASM macro
01a,12may01,g_h  create from ppmc7xx.h rev 01b
*/

/*
This file contains I/O addresses and related constants for the board.
*/

#ifndef	__INCwrSbc7410h
#define	__INCwrSbc7410h

#ifdef __cplusplus
extern "C" {
#endif

#include "gt64260Def.h"

/* Local I/O address map */

#define SDRAM_BASE_ADS		   0x00000000
#define USR_LED_BASE_ADRS	   0x1c000000
#define USR_LED_REG_SIZE	   0x00000001
#define HW_REV_BASE_ADRS	   0x1c000001
#define HW_REV_REG_SIZE	       0x00000001
#define CTRL_REG_BASE_ADRS     0x1c000002
#define CTRL_REG_SIZE          0x00000001
#define FPGA_REG_SIZE		   0x00001000 /* 4K, min page size */
#define NS16550_BASE_ADRS	   0x1d000000
#define NS16550_REG_SIZE	   0x00001000
#define FLASH_BASE_ADRS        0xFF000000
#define FLASH_MEM_SIZE         0x00f00000 /* 15MB */
#define TFFS_FLASH_SIZE        0x00800000 /* 8MB, must be a power of 2 (1,2,4,8,16,32...) */
#define INCLUDE_MTD_USR
#define MTD_USR_IDENTIFY       strataFlashIdentify

#define FLASH_BASE_ADRS0	   0xff000000
#define FLASH_SIZE0			   0x00800000 /* 8 MB */

#define FLASH_BASE_ADRS1       0xff800000
#define FLASH_SIZE1			   0x00400000 /* 4 MB */

#define FLASH_BASE_ADRS2	   0xffc00000
#define FLASH_SIZE2			   0x00200000 /* 2 MB */

#define FLASH_BASE_ADRS3	   0xffe00000
#define FLASH_SIZE3			   0x00100000 /* 1MB */

#define MAILBOX_BASE_ADRS      0x1c800000
#define MAILBOX_REG_SIZE       0x00010000
#define EEPROM_BASE_ADRS       0x1c010000
#define EEPROM_REG_SIZE        0x00002000
#define GT64260_BASE_ADRS      0x14000000
#define GT64260_REG_SIZE	   0x00010000 /* 64 KB */


#define BUS_TYPE		BUS_TYPE_PCI    /* board bus interface  */

/* Timer constants */

#define	SYS_CLK_RATE_MIN  	  3    /* minimum system clock rate */
#define	SYS_CLK_RATE_MAX  	  5000 /* maximum system clock rate */
#define	AUX_CLK_RATE_MIN  	  3    /* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX  	  5000 /* maximum auxiliary clock rate */

/* create a single macro INCLUDE_MMU */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
  #define INCLUDE_MMU
#endif

/* Only one can be selected, FULL overrides BASIC */

#ifdef INCLUDE_MMU_FULL
  #undef INCLUDE_MMU_BASIC
#endif

/* serial ports (COM1,COM2) */

#define N_SIO_CHANNELS		  	1 /* Number of serial I/O channels */
#define N_UART_CHANNELS		  	N_SIO_CHANNELS
#define COM1_BASE_ADR           NS16550_BASE_ADRS
#define COM1_INT_VEC            INT_VEC_GPP7_0
#define COM1_INT_LVL   		  	INT_LVL_GPP7_0
#define UART_XTAL_FREQ		  	3686400
#undef  CONSOLE_BAUD_RATE
#define CONSOLE_BAUD_RATE	  	9600
#define UART_REG_ADDR_INTERVAL  1

/*
 * PCI part 
 */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define PCISWAP(x)	          LONGSWAP(x) /* processor big endian */
#define BYTE_SWAP_16_BIT(x)       ((LSB(x) << 8) | MSB(x))
#else
#define PCISWAP(x)	          (x) /* processor little endian */
#define BYTE_SWAP_16_BIT(x)       (x)
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

/*
 * mpc107 PCI Configuration Defines
 */
#define HOST_BRIDGE_NUM		  0
#define HOST_BRIDGE_IDSEL	  0

#define PCI_ADDRESS_REGISTER	0xFEC00000 /* PCI Address Register  */
#define PCI_DATA_REGISTER	  	0xFEE00000 /* PCI Data Register     */

#define PCI_IO_BASE		  		0x20000000 /* PCI IO Start Address  */
#define PCI_IO_SIZE		  		0x02000000 /* PCI IO Size - 32M     */
#define PCI_MEM_BASE			0x22000000 /* PCI MEM Start Address */
#define PCI_MEM_SIZE			0x08000000 /* PCI MEM Size	- 32M * 4  */

#define PCI_IO_END		  		(PCI_IO_BASE + PCI_IO_SIZE - 1)
#define PCI_MEM_END		  		(PCI_MEM_BASE + PCI_MEM_SIZE - 1)

/*
 * BRD_PCIMEM_CPU2PCI(addr, bridge)
 *     mapping the PCI memory address from CPU view to PCI view
 *
 * BRD_PCIIO_CPU2PCI(addr, bridge)
 *     mapping the PCI IO address from CPU view to PCI view
 *
 * BRD_PCIIO_PCI2CPU(addr, bridge)
 *     mapping the PCI IO address from PCI view to CPU view
 *
 * BRD_PCIMEM_PCI2CPU(addr, bridge)
 *     mapping the PCI memory address from PCI view to CPU view
 */
#define BRD_PCIIO_CPU2PCI(addr, bridge)  ((ULONG)addr & 0x00ffffff)
#define BRD_PCIIO_PCI2CPU(addr, bridge)  ((ULONG)addr | PCI_IO_BASE)
#define BRD_PCIMEM_CPU2PCI(addr, bridge) ((ULONG)addr)
#define BRD_PCIMEM_PCI2CPU(addr, bridge) ((ULONG)addr)

#define CPU2DEV_ADDR(x)		PCISWAP( (BRD_PCIMEM_CPU2PCI(x,0)) )
#define DEV2CPU_ADDR(x)		(void*)BRD_PCIMEM_PCI2CPU(PCISWAP((x)),0)

/*
 * PCI Autoconfig Configuration Defines - Mandatory stuff that must be defined in
 * order to use vWare's PCI Autoconfig.
 */
#undef  PCI_MAX_DEV	
#define PCI_MAX_DEV		  		21
#undef  PCI_MAX_BUS
#define PCI_MAX_BUS		  		2
#undef  PCI_MAX_FUNC
#define PCI_MAX_FUNC	  		8

#if defined(INCLUDE_PCI_STANDALONE)
  #define PCI_PP_MEM_START	  0x22000000 /* PCI Auto Config Memory Start Address */
#elif defined(INCLUDE_PCI_CARD_IN_BACKPLANE)
  #define PCI_PP_MEM_START	  0x12000000 /* PCI Auto Config Memory Start Address */
#endif
  #define PCI_PP_MEM_SIZE	  0x08000000 /* PCI Auto Config Memory Size	     */
#if defined(INCLUDE_PCI_STANDALONE)
  #define PCI_PP_IO_START	  0x20000000 /* PCI Auto Config IO Start Address     */
#elif defined(INCLUDE_PCI_CARD_IN_BACKPLANE)
  #define PCI_PP_IO_START	  0x10000000 /* PCI Auto Config IO Start Address     */
#endif

#define PCI_PP_IO_SIZE		  0x02000000 /* PCI Auto Config IO Size 32MB          */

#define PCI_PP_IO16_START	  0xFE008000
#define PCI_PP_IO16_SIZE	  (0xFE010000-PCI_PP_IO16_START) /* 64KB */


#define CPU_PCI_MEM_ADRS	  PCI_PP_MEM_START /* 32 bit prefetchable memory */
						   /* base addres of PCI mem */
#define CPU_PCI_MEM_SIZE	  PCI_PP_MEM_SIZE  /* 32 bit prefetchable memory size  */
#define CPU_PCI_CNFG_ADRS	  0xF0000000       /* 32 bit PCI plag & play memory */
						   /* base addres of PCI conf */
#define CPU_PCI_CNFG_SIZE	  0x02000000       /* 32 bit PCI plag & play memory size  */
#define CPU_PCI_IO_ADRS	      PCI_IO_BASE      /* base addres of PCI IO */
#define CPU_PCI_IO_SIZE	      0x01000000  

#define PCI_MSTR_MEMIO_LOCAL  PCI_PP_MEM_START /* CPU to PCI memio */
#define PCI_MSTR_MEMIO_BUS	  PCI_PP_MEM_START /* PCI bus view */
#define PCI_SLV_MEM_LOCAL	  0x00000000 

/* PCI (non-prefetchable) memory adrs to CPU (60x bus) adrs */

#define PCI_MEMIO2LOCAL(x)        ((int)(x)+PCI_MSTR_MEMIO_LOCAL-PCI_MSTR_MEMIO_BUS)


/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x)        ((int)(x) + PCI_SLV_MEM_LOCAL)

#define MPC107PCI_BRIDGE	  	  0
#define INTEL21154PCI_BRIDGE      1

#define PCI_INTA_MPC107_IRQ0      0
#define PCI_INTB_MPC107_IRQ1      1
#define PCI_INTC_MPC107_IRQ2      2
#define PCI_INTD_MPC107_IRQ3      3

/* NvRam on FLASH macros */

#define ONE_K			  	  1024
#define FLASH_SECTOR_SIZE	  (128 * ONE_K * 2)

/* Osillator macros */

#define OSCILLATOR_165MHZ        165000000 /* Bus Speeds */
#define OSCILLATOR_100MHZ        100000000
#define OSCILLATOR_99MHZ          99000000
#define OSCILLATOR_66MHZ          66000000
#define OSCILLATOR_33MHZ          33000000
#define OSCILLATOR_132MHZ        132000000
#define OSCILLATOR_148_5MHZ      148500000
#define OSCILLATOR_231MHZ        231000000
#define OSCILLATOR_247_5MHZ      247500000
#define OSCILLATOR_297MHZ        297000000

#define SYS_CPU_FREQ             (OSCILLATOR_148_5MHZ)
#define TCLK_FREQ				 (OSCILLATOR_100MHZ)

/* decrementer constants */

#define DEC_CLOCK_FREQ            SYS_CPU_FREQ/2
#define DEC_CLK_TO_INC	          3

#define SYS_CLK_TICKS_PER_SECOND  60      /* default 60 ticks/second */

#define DELTA(a,b)     		  (abs((int)a - (int)b))

/* PCI Bus Frequency */
#define DEFAULT_BUS_CLK_FREQ	  33000000 /* 33.00 Mhz  */

/*
 * Miscellaneous definitions go here. For example, macro definitions
 * for various devices.						   
 */

#if CPU==PPC603
  #define WRONG_CPU_MSG "PPC603 VxWorks image cannot run on a PPC604!\n";
#else
  #define WRONG_CPU_MSG "Unsupported processor type for this board.\n";
#endif

#define CPU_TYPE		  ((vxPvrGet() >> 12) & 0xffff)
#define CPU_TYPE_750   		  0x80 /* PPC 750 CPU */
#define CPU_TYPE_755   		  0x83 /* PPC 755 CPU */