sysmotfccend.c

WINDRIVER 8260 ATM BSP

*
* sysMiiPhySpeed - check Speed
*
* This routine checks the link Speed
*
* RETURNS: 2 if 1000, 1 if 100 or 0 if 10 BPS.
*/

LOCAL STATUS sysMiiPhySpeed
    (
    PHY_INFO * pPhyInfo,
    int      * pSpeed
    )
    {
    UINT16 miiStat;
    int    retVal;

    MII_READ(pPhyInfo->phyAddr,17,&miiStat,retVal);
    
    if (retVal == OK)
        {
        *pSpeed = (miiStat & 0x4000) ? 1 : 0;
        }
    return retVal;
    }


/***********************************************************************
*
* sysMiiInt - MII interrupt service routine
*
* This routine check if the link up or down and update a flag
*
* RETURNS: None.
*/

LOCAL void sysMiiInt
    (
    PHY_INFO * pPhyInfo
    )
    {
    UINT16 miiIntStatusReg;
    int    tmp;

    /* Clear MII interrupt by reading Int status reg */
    MII_READ(pPhyInfo->phyAddr,19,&miiIntStatusReg,tmp);
    
    if ( sysMotFccFuncs[SYS_MII_PHY_INT] != NULL )
        {
        (* sysMotFccFuncs[SYS_MII_PHY_INT] )(pPhyInfo->pDrvCtrl);
        }
    }

/***********************************************************************
*
* sysMiiPhyInit - initialize and configure the PHY devices
*
* This routine scans, initializes and configures the PHY device.
*
* RETURNS: OK, or ERROR.
*/

LOCAL STATUS sysMiiPhyInit
    (
    PHY_INFO * pPhyInfo
    )
    {
    int    retVal,tmp;
    UINT16 miiIntEnableReg;
    
    retVal = miiPhyInit (pPhyInfo);

    if (retVal == OK)
        {
        MII_READ(pPhyInfo->phyAddr,18,&miiIntEnableReg,tmp);

        if (tmp == OK)
            {
            intConnect (INUM_TO_IVEC(INUM_IRQ6),sysMiiInt,(int)pPhyInfo);
            miiIntEnableReg = 0x12;
            MII_WRITE(pPhyInfo->phyAddr, 18, miiIntEnableReg, tmp);
            if (tmp == OK)
                {
                intEnable (INUM_IRQ6);
                }
            }
        }
    return retVal;
    }

/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/
 
STATUS sysFccEnetEnable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    volatile UINT32 tmp;
    int             intLevel;

    intLevel = intLock ();

    /* set Port B and C to use MII signals */

    *M8260_IOP_PBPAR(immrVal) &= ~(PB15 | PB14);    /* clear PAR bits for xcvr RST and PWRDWN pins */
    *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14);    /* make them outputs */

    tmp = *M8260_IOP_PBDAT(immrVal);            /* get current port B data */
    tmp &= ~(PB14);                 /* drive the active high PWRWN pin low */
    tmp &= ~(PB15);                 /* drive the active low RST low too, for now */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    *M8260_IOP_PCPAR(immrVal) |=  (PC19 | PC18);
    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCSO(immrVal)  &= ~(PC19 | PC18);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC19 | PC18);

    *M8260_IOP_PBPAR(immrVal) |=  (PB31 | PB30 | PB29 | PB28 | PB27 | PB26 | PB25 |
                                   PB24 | PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBDIR(immrVal) |=  (PB31 | PB29 | PB25 | PB24 | PB23 | PB22);
    *M8260_IOP_PBDIR(immrVal) &= ~(PB30 | PB28 | PB27 | PB26 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBSO(immrVal)  &= ~(PB31 | PB30 | PB28 | PB27 | PB26 | PB25 | PB24 | 
                                   PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBSO(immrVal)  |=  (PB29);

    /* connect FCC2 clocks */

    *M8260_CMXFCR (immrVal)  |= (0x00250000);
    *M8260_CMXFCR (immrVal)  &= ~(0x00400000);

    tmp = *M8260_IOP_PBDAT(immrVal); /* get current port B data */
    tmp |=  (PB15);                  /* drive the active low RST high */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    intUnlock (intLevel);
    
    taskDelay (sysClkRateGet() >> 2);
    
    return(OK);
    }

/*********************************************************************** 
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/
 
STATUS sysFccEnetDisable
    (
    UINT32  immrVal,    /* base address of the on-chip RAM */
    UINT8   fccNum  /* FCC being used */
    )
    {
    volatile UINT32 tmp;
    int             intLevel;

    intLevel = intLock ();
 
    /* 
     * configure all Port B and C pins previously used as general 
     * purpose input pins 
     */

    *M8260_IOP_PBPAR(immrVal) &= ~(PB15 | PB14);    /* clear PAR bits for xcvr RST and PWRDWN pins */
    *M8260_IOP_PBDIR(immrVal) |=  (PB15 | PB14);    /* make them outputs */

    tmp = *M8260_IOP_PBDAT(immrVal);        /* get current port B data */
    tmp |=  (PB14);         /* drive the active high PWRWN pin high */
    tmp &= ~(PB15);         /* drive the active low RST low too */
    *M8260_IOP_PBDAT(immrVal) = tmp;

    *M8260_IOP_PCPAR(immrVal) &= ~(PC19 | PC18);

    *M8260_IOP_PCDIR(immrVal) &= ~(PC10);

    *M8260_IOP_PBPAR(immrVal) &= ~(PB31 | PB30 | PB29 | PB28 | PB27 | PB26 | PB25 |
                                   PB24 | PB23 | PB22 | PB21 | PB20 | PB19 | PB18);
    *M8260_IOP_PBDIR(immrVal) &= ~(PB31 | PB29 | PB25 | PB24 | PB23 | PB22);

    /* Disable the interrupt */
    intDisable (INUM_FCC2);

    intUnlock (intLevel);
    
    return(OK);
    }

#ifndef NSDELAY
#define MOTOROLA_FCC_LOOP_NS 2

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);               \
                                                                        \
    for (nx = 0; nx < loop; nx++);                                      \
    }
#endif /* NSDELAY */

/*********************************************************************** 
*
* sysFccEnetAddrGet - get the hardware Ethernet address
*
* This routine provides the six byte Ethernet hardware address that will be
* used by each individual FCC device unit.  This routine must copy
* the six byte address to the space provided by <addr>.
*
* RETURNS: OK, or ERROR if the Ethernet address cannot be returned.
*/
STATUS sysFccEnetAddrGet
    (
    int     unit, 
    UCHAR * pAddr
    )
    {
    /* need extra room for a 'EOS' -- driver may not provide it */
    UINT8   eAdrs[MAC_ADRS_LEN + 2];
    STATUS  status;

    status = sysEnetAddrGet (unit,eAdrs); 

    if (status == OK)
        {
        memcpy(pAddr,eAdrs,MAC_ADRS_LEN);
        }
    return status;
    }


/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
    (
    UINT32  immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT32   bitVal          /* the bit being written */
    )
    {
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) |= (PC10 | PC9);
    *M8260_IOP_PCDAT(immrVal) |= (PC10);

    switch (bitVal)
    {
    case 0:
        *M8260_IOP_PCDAT(immrVal) &= ~(PC9);
        break;
    case 1:
        *M8260_IOP_PCDAT(immrVal) |= (PC9);
        break;
    case ((INT32) NONE):
        /* put it in high-impedance state */
        *M8260_IOP_PCDIR(immrVal) &= ~(PC9);
        break;
    default:
        return (ERROR);
    }

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    return (OK);
    }

/*********************************************************************** 
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,        /* base address of the on-chip RAM */
    UINT8   fccNum,     /* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC9);

    *M8260_IOP_PCDIR(immrVal) |= (PC10);
    *M8260_IOP_PCDAT(immrVal) |= (PC10);

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(PC10);

    NSDELAY (200);

    /* we can now read the MDIO data on PC9 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC9)) >> 22;
 
    return (OK);
    }

#endif /* INCLUDE_MOTFCCEND */