rominit.s

WINDRIVER 8260 ATM BSP

	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_MBMR(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_MCMR(r4)

	li	    r5,0x3200
	sth		r5,INIT_MPTPR(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_MDR(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_PSDMR(r4)

	li		r5,0x08
	stb		r5,INIT_PURT(r4)

	li		r5,0x0E
	stb		r5,INIT_PSRT(r4)

	li		r5,0x00
	stb		r5,INIT_LURT(r4)

	li		r5,0x00
	stb		r5,INIT_LSRT(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_PCIBR0(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_PCIBR1(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_PCIMSK0(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_PCIMSK1(r4)

	li		r5,0x0000
	sth		r5,INIT_RMR(r4)

	bl	memcSdram60xBusInit

	bl	memcSdramLocalBusInit

	mtspr	LR,r30
	bclr	20,0

/******************************************************************************
*
* romChipSelectInit - initialize the Scout chip select
*
*
* RETURNS: N/A.
*/

romChipSelectInit:

	mfspr	r29,LR

	/****************************************************
	 * CS0/1/6: 64Meg, 32-bit Flash SIMM or 2Meg, 8-bit Flash.
	 ****************************************************/

#ifdef SIMM_FLASH_CS0
	lis	    r5,HIADJ(0xFC000856) /* CS0 to SIMM FLASH */
	addi	r5,r5,LO(0xFC000856)
	stw		r5,INIT_OR0(r4)

	lis	    r5,HIADJ(0xFC001801)
	addi	r5,r5,LO(0xFC001801)
	stw		r5,INIT_BR0(r4)

	lis	    r5,HIADJ(0xFC000856) /* CS1 to SIMM FLASH */
	addi	r5,r5,LO(0xFC000856)
	stw		r5,INIT_OR1(r4)

	lis	    r5,HIADJ(0xFC201801)
	addi	r5,r5,LO(0xFC201801)
	stw		r5,INIT_BR1(r4)

	lis	    r5,HIADJ(0xFFE00060) /* CS6 to ON Board FLASH */
	addi	r5,r5,LO(0xFFE00060)
	stw		r5,INIT_OR6(r4)

	lis	    r5,HIADJ(0xE0000801)
	addi	r5,r5,LO(0xE0000801)
	stw		r5,INIT_BR6(r4)
#endif /* SIMM_FLASH_CS0 */

#ifdef LOCAL_FLASH_CS0
	lis	    r5,HIADJ(0xFE000856) /* CS0 to On Board FLASH */
	addi	r5,r5,LO(0xFE000856)
	stw		r5,INIT_OR0(r4)

	lis	    r5,HIADJ(0xFE000801) 
	addi	r5,r5,LO(0xFE000801)
	stw		r5,INIT_BR0(r4)

	lis	    r5,HIADJ(0xFE000856) /* CS1 to SIMM FLASH */
	addi	r5,r5,LO(0xFE000856)
	stw		r5,INIT_OR1(r4)

	lis	    r5,HIADJ(0xE2001801)
	addi	r5,r5,LO(0xE2001801)
	stw		r5,INIT_BR1(r4)

	lis	    r5,HIADJ(0xFE000856) /* CS6 to SIMM FLASH */
	addi	r5,r5,LO(0xFE000856)
	stw		r5,INIT_OR6(r4)

	lis	    r5,HIADJ(0xE0001801)
	addi	r5,r5,LO(0xE0001801)
	stw		r5,INIT_BR6(r4)
#endif /* LOCAL_FLASH_CS0 */


	/****************************************************
	 * CS1: 64Meg, 32-bit Flash SIMM
	 ****************************************************/

    /* Part of CS0 */

	/****************************************************
	 * CS2/CS3: 60x Bus SRAM.
	 ****************************************************/

	lis	    r5,HIADJ(0xF80024C0)
	addi	r5,r5,LO(0xF80024C0)
	stw		r5,INIT_OR2(r4)

	lis	    r5,HIADJ(0x00000041)
	addi	r5,r5,LO(0x00000041)
	stw		r5,INIT_BR2(r4)

	lis	    r5,HIADJ(0xF80024C0)
	addi	r5,r5,LO(0xF80024C0)
	stw		r5,INIT_OR3(r4)

	lis	    r5,HIADJ(0x08000041)
	addi	r5,r5,LO(0x08000041)
	stw		r5,INIT_BR3(r4)

	/****************************************************
	 * CS4: Local Bus SRAM.
	 ****************************************************/

	lis	    r5,HIADJ(0xFF0030C0)
	addi	r5,r5,LO(0xFF0030C0)
	stw		r5,INIT_OR4(r4)

	lis	    r5,HIADJ(0x10001861)
	addi	r5,r5,LO(0x10001861)
	stw		r5,INIT_BR4(r4)

	/****************************************************
	 * CS5: 32Kb, 8-bit, EEPROM.
	 ****************************************************/

	lis	    r5,HIADJ(0xFFFC03F6)
	addi	r5,r5,LO(0xFFFC03F6)
	stw		r5,INIT_OR5(r4)

	lis	    r5,HIADJ(0x22000801)
	addi	r5,r5,LO(0x22000801)
	stw		r5,INIT_BR5(r4)

	/****************************************************
	 * CS6: 16Meg, 8-bit Flash SIM or 2Meg, 8-bit Flash.
	 ****************************************************/

    /* Part of CS 0 */

	/****************************************************
	 * CS7: User Switches/User LEDs
	 ****************************************************/

	lis	    r5,HIADJ(0xFFFF03F6)
	addi	r5,r5,LO(0xFFFF03F6)
	stw		r5,INIT_OR7(r4)

	lis	    r5,HIADJ(0x21000801)
	addi	r5,r5,LO(0x21000801)
	stw		r5,INIT_BR7(r4)

	/****************************************************
	 * CS8: Disabled
	 ****************************************************/

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_OR8(r4)

	lis	    r5,HIADJ(0x00000000)
	addi	r5,r5,LO(0x00000000)
	stw		r5,INIT_BR8(r4)

	/****************************************************
	 * CS9:
	 ****************************************************/

	lis	    r5,HIADJ(0xFFFF0000)
	addi	r5,r5,LO(0xFFFF0000)
	stw		r5,INIT_OR9(r4)

	lis	    r5,HIADJ(0x60000081)
	addi	r5,r5,LO(0x60000081)
	stw		r5,INIT_BR9(r4)

	/****************************************************
	 * CS10:
	 ****************************************************/

	lis	    r5,HIADJ(0xFFFF0000)
	addi	r5,r5,LO(0xFFFF0000)
	stw		r5,INIT_OR10(r4)

	lis	    r5,HIADJ(0x700000A1)
	addi	r5,r5,LO(0x700000A1)
	stw		r5,INIT_BR10(r4)

	/****************************************************
	 * CS11:
	 ****************************************************/

	lis	    r5,HIADJ(0xFFFF0000)
	addi	r5,r5,LO(0xFFFF0000)
	stw		r5,INIT_OR11(r4)

	lis	    r5,HIADJ(0x800000C1)
	addi	r5,r5,LO(0x800000C1)
	stw		r5,INIT_BR11(r4)

	mtspr	LR,r29
	bclr	20,0

/******************************************************************************
*
* memcSdram60xBusInit - initialize 60x Bus SDRAM.
*
*
* RETURNS: N/A.
*/

memcSdram60xBusInit:

	mfspr	r29,LR

	lis		r5,0x0000
	ori		r5,r5,0x0000

	/**********************************************
	 * Initialize 60x Bus SDRAM.
	 **********************************************/

	li		r6,0x0E
	stb		r6,INIT_PSRT(r4)

	lis	    r6,HIADJ(0x2252B452)
	addi	r6,r6,LO(0x2252B452)
	stw		r6,INIT_PSDMR1(r4)

	li		r6,0xFF
	stb		r6,INIT_MEM0(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM0(r5)

	lis	    r6,HIADJ(0x0A52B452)
	addi	r6,r6,LO(0x0A52B452)
	stw		r6,INIT_PSDMR2(r4)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM1(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM1(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM2(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM2(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM3(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM3(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM4(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM4(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM5(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM5(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM6(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM6(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM7(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM7(r5)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM8(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM8(r5)

	lis	    r6,HIADJ(0x1A52B452)
	addi	r6,r6,LO(0x1A52B452)
	stw		r6,INIT_PSDMR3(r4)

	li		r6,0xFF
	lis     r5,0x0
	stb		r6,INIT_MEM9(r5)

	li		r6,0xFF
	lis		r5,0x0800		
	stb		r6,INIT_MEM9(r5)

	lis	    r6,HIADJ(0x4252B452)
	addi	r6,r6,LO(0x4252B452)
	stw		r6,INIT_PSDMR4(r4)

	mtspr	LR,r29
	bclr	20,0

/******************************************************************************
*
* memcSdramLocalBusInit - initialize Local Bus SDRAM.
*
*
* RETURNS: N/A.
*/

memcSdramLocalBusInit:

	mfspr	r29,LR

	lis		r5,0x0400
	ori		r5,r5,0x0000

	/**********************************************
	 * Initialize Local Bus SDRAM.
	 **********************************************/

	li		r6,0x0E
	stb		r6,INIT_LSRT(r4)

	lis	    r6,HIADJ(0x2866A552)
	addi	r6,r6,LO(0x2866A552)
	stw		r6,INIT_LSDMR1(r4)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM0(r5)

	lis	    r6,HIADJ(0x0866A552)
	addi	r6,r6,LO(0x0866A552)
	stw		r6,INIT_LSDMR2(r4)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM1(r5)

	li		r6,0xFF	
	lis		r5,0x1000
	stb		r6,INIT_MEM2(r5)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM3(r5)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM5(r5)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM6(r5)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM7(r5)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM8(r5)

	lis	    r6,HIADJ(0x1866A552)
	addi	r6,r6,LO(0x1866A552)
	stw		r6,INIT_LSDMR3(r4)

	li		r6,0xFF
	lis		r5,0x1000
	stb		r6,INIT_MEM9(r5)

	lis	    r6,HIADJ(0x4066A552)
	addi	r6,r6,LO(0x4066A552)
	stw		r6,INIT_LSDMR4(r4)

	mtspr	LR,r29
	bclr	20,0

/******************************************************************************
*
* romCacheInit - 
*
*
*
*/

romCacheInit:
	/* turn the instruction cache ON for faster FLASH ROM boots */

	mfspr	r5,HID0
	ori	    r5,r5,_PPC_HID0_ICE
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0,r5
	sync
	isync
	bclr	20,0