syslib.c

WINDRIVER ADS8260 BSP

void sysBusClearTas
    (
     volatile char * address	/* address to be tested-and-cleared */
    )
    {
    } 

/*******************************************************************************
*
* vxImmrGet - return the current IMMR value
*
* This routine returns the current IMMR value
*
* RETURNS: current IMMR value
*
*/

UINT32  vxImmrGet (void)
    {
    return ((*immrAddress) & IMMR_ISB_MASK);
    }

#ifdef INCLUDE_MOTFCCEND
 
/*******************************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/
 
STATUS sysFccEnetEnable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
    {
    /* enable the Ethernet tranceiver for the FCC */

    /* de-assert the reset signal */

    *BCSR1 |= BCSR1_FETH_RST_L;

    /* assert the enable signal */

    *BCSR1 &= ~BCSR1_FETH_IEN_L;
 
    /* introduce a little delay */
 
    taskDelay (sysClkRateGet ());
 
    /* set Port B and C to use MII signals */

    *M8260_IOP_PCPAR(immrVal) |= (0x00003000);	/* (19|18) */
    *M8260_IOP_PCPAR(immrVal) &= ~(0x00600000);	/* ~(10|9) */
    *M8260_IOP_PCSO(immrVal) &= ~(0x00003000);	/* ~(19|18) */
    *M8260_IOP_PCDIR(immrVal) &= ~(0x00003000);	/* ~(19|18) */

    *M8260_IOP_PBPAR(immrVal) |= (0x00003fff);	/* (31|30|29|28|27|26|25|24
						23|22|21|20|19|18) */
    *M8260_IOP_PBDIR(immrVal) |= (0x000003c5);	/* (31|29|25|24|23|22) */
    *M8260_IOP_PBDIR(immrVal) &= ~(0x00003c3a);	/* ~(30|28|27|26|21|20|19|18) */
    *M8260_IOP_PBSO(immrVal) &= ~(0x00003ffb);	/* ~(31|30|28|27|26|25|24|23|
						 22|21|20|19|18) */
    *M8260_IOP_PBSO(immrVal) |= (0x00000004);	/* (29) */

    /* connect FCC2 clocks */

    *M8260_CMXFCR (immrVal)  |= (M8260_CMXFCR_R2CS_CLK13 
				 | M8260_CMXFCR_T2CS_CLK14);

    /* NMSI mode */

    *M8260_CMXFCR (immrVal)  &= ~(M8260_CMXFCR_FC2_MUX);         

    return (OK);
    }
 
/*******************************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/
 
STATUS sysFccEnetDisable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
    {
    int intLevel = intLock();
 
    /* 
     * configure all Port B and C pins previously used as general 
     * purpose input pins 
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(0x00003000);	/* (19|18) */

    *M8260_IOP_PCDIR(immrVal) &= ~(0x00200000);	/* (10) */

    *M8260_IOP_PBPAR(immrVal) &= ~(0x00003fff);	/* (31|30|29|28|27|26|25|24
						23|22|21|20|19|18) */
    *M8260_IOP_PBDIR(immrVal) &= ~(0x000003c5);	/* (31|29|25|24|23|22) */

    /* disable the Ethernet tranceiver for the FCC */

    /* de-assert the enable signal */

    *BCSR1 |= BCSR1_FETH_IEN_L;

    /* assert the reset signal */

    *BCSR1 &= ~BCSR1_FETH_RST_L;
 
    intUnlock (intLevel);
 
    return (OK);
    }
 
/*******************************************************************************
*
* sysFccEnetAddrGet - get the hardware Ethernet address
*
* This routine provides the six byte Ethernet hardware address that will be
* used by each individual FCC device unit.  This routine must copy
* the six byte address to the space provided by <addr>.
*
* RETURNS: OK, or ERROR if the Ethernet address cannot be returned.
*/
 
STATUS sysFccEnetAddrGet
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    UCHAR *     addr            /* where to copy the Ethernet address */
    )
    {
    bcopy ((char *) sysFccEnetAddr, (char *) addr, sizeof (sysFccEnetAddr));
 
    return (OK);
    }


/*******************************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    UINT16	command
    )
    {
    return (OK);
    }

#ifndef NSDELAY
#define MOT_FCC_LOOP_NS 1

#define NSDELAY(nsec)                                                   \
    {                                                                   \
    volatile int nx = 0;                                                \
    volatile int loop = (int)(nsec*MOT_FCC_LOOP_NS);                    \
                                                                        \
    for (nx = 0; nx < loop; nx++);                                      \
    }
#endif /* NSDELAY */

/**************************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
    {
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We need to keep the same data
     * on MDIO for at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(0x00600000);	/* ~(10|9) */
    *M8260_IOP_PCDIR(immrVal) |= (0x00600000);	/* (10|9) */
    *M8260_IOP_PCDAT(immrVal) |= (0x00200000);	/* (10) */

    switch (bitVal)
	{
	case 0:
	    *M8260_IOP_PCDAT(immrVal) &= ~(0x00400000);	/* ~(9) */
	    break;

	case 1:
	    *M8260_IOP_PCDAT(immrVal) |= (0x00400000);	/* (9) */
	    break;

	case ((INT32) NONE):
	    /* put it in high-impedance state */

	    *M8260_IOP_PCDIR(immrVal) &= ~(0x00400000);	/* ~(9) */

	    break;

	default:
	    return (ERROR);
	}

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(0x00200000);	/* ~(10) */

    NSDELAY (200);

    return (OK);
    }
 
/**************************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
    {
    /* 
     * we create the timing reference for transfer of info on the MDIO line 
     * MDIO is mapped on PC9, MDC on PC10. We can read data on MDIO after
     * at least 400 nsec.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(0x00600000);	/* ~(10|9) */
    *M8260_IOP_PCDIR(immrVal) &= ~(0x00400000);	/* ~(9) */

    *M8260_IOP_PCDIR(immrVal) |= (0x00200000);	/* (10) */
    *M8260_IOP_PCDAT(immrVal) |= (0x00200000);	/* (10) */

    /* delay about 200 nsec. */

    NSDELAY (200);

    /* now we toggle the clock and delay again */

    *M8260_IOP_PCDAT(immrVal) &= ~(0x00200000);	/* (10) */

    NSDELAY (200);

    /* we can now read the MDIO data on PC9 */

    *bitVal = (*M8260_IOP_PCDAT(immrVal) & (0x00400000)) >> 22;
 
    return (OK);
    }
 
/**************************************************************************
*
* sysMiiOptRegsHandle - handle some MII optional registers
*
* This routine handles some MII optional registers in the PHY 
* described by <pPhyInfo>.
*
* In the case of the ads8260, the PHY that implements the physical layer 
* for the FCC is an LXT970. The default values for some of its chip-specific
* registers seem to be uncompatible with 100Base-T operations. This routine 
* is expected to perform any PHY-specific functions required to bring the
* PHY itself to a state where 100Base-T operations may be possible.
*
* SEE ALSO: miiLib, motFccEnd.
*
* RETURNS: OK, or ERROR.
*/
STATUS sysMiiOptRegsHandle
    (
    PHY_INFO	* pPhyInfo		/* PHY control structure pointer */
    )
    {
    int		retVal;			/* a convenience */

    /* 
     * the LXT970 on the ads8260 comes up with the scrambler
     * function disabled, so that it will not work in 100Base-T mode.
     * write 0 to the configuration register (address 0x13) 
     * to enable the scrambler function 
     */

    MII_WRITE (pPhyInfo->phyAddr, 0x13, 0x0, retVal);
    if (retVal != OK)
        return (ERROR);

    return (OK);
    }
#endif	/* INCLUDE_MOTFCCEND */

/**************************************************************************
*
* sysFlashLED - flash one of the signal lamps
*
* This routine will flash the indicated signal lamp for about 1/4 second
*
* SEE ALSO:
*
* RETURNS: NA
*/
void sysFlashLED
    (
    int LED	/* bitmap of LED to flash */
    )
    {

    sysControlLED(LED, BCSR0_LED_ON);

    taskDelay(15);

    sysControlLED(LED, BCSR0_LED_OFF);

    }

/**************************************************************************
*
* sysControlLED - control one of the signal lamps
*
* This routine will turn the indicated signal lamp on or off, as
* requested
*
* SEE ALSO:
*
* RETURNS: NA
*/

void sysControlLED
    (
    int LED, 	/* bitmap of LED to control */
    int on	/* if TRUE turn LED ON; otherwise, turn LED OFF */
    )
    {

    CACHE_PIPE_FLUSH();			/* always before first read */

    if (on)
	*(UINT32 *)BCSR0 &= ~LED; /* clearing bit turns LED on */
    else
	*(UINT32 *)BCSR0 |= LED; /* setting bit turns LED off */

    }