ads8260.h

WINDRIVER ADS8260 BSP

/* ads8260.h - Motorola MPC8260 ADS board header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01j,12jun02,kab  SPR 74987: cplusplus protection
01i,22oct01,jrs  Upgrade to veloce - changed arch from PPCEC603 to PPC603.
		 set DEC_CLOCK_FREQ to OSCILLATOR_FREQ
		 removed MOD_CK, MOD_CK_H, and FREQ_40_MHZ definitions,
		 added Clock Speed and source definitions - SPR#66989
01h,20oct01,yvp  Corrected CPU type to PPC603 from PPCC603
01f,14mar00,ms_  add support for PILOT revision of board
01e,16sep99,ms_  get some .h files from h/drv instead of locally
01d,15jul99,ms_  make compliant with our coding standards
01c,17apr99,ms_  remove unnecessary macros
01b,17apr99,ms_  final EAR cleanup
01a,08jan99,ms_  adapted from ads860.h
*/

/*
This file contains I/O addresses and related constants for the
Motorola MPC8260 ADS board. 
*/

#ifndef	INCads8260h
#define	INCads8260h

#ifdef __cplusplus
    extern "C" {
#endif

#include "drv/mem/memDev.h"
#include "drv/intrCtl/m8260IntrCtl.h"

#define BUS	0				/* bus-less board */

#undef  CPU
#define CPU	PPC603				/* CPU type */

#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */

#define IMMR_ADDRESS_RESET_VALUE           0x047101a8

/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ	OSCILLATOR_FREQ

/* Internal Memory Map base Address */

#define INTERNAL_MEM_MAP_ADDR		(IMMR_ADDRESS_RESET_VALUE & 0xfffe0000)	
#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes */
#define IMMR_ISB_MASK		0xfffe0000	/* Internal Space Base mask */
#define IMMR_PARTNUM_MASK	0x0000ff00	/* Part Number mask */
#define IMMR_MASKNUM_MASK	0x000000ff	/* Mask Number mask */

/* Board Status and Control Registers - unique to ADS */

#define	BCSR_BASE_ADRS	0x04500000	/* BCSR base address */
#define BCSRS_SIZE      0x00010000      /* 64K of address space */

#ifdef _ASMLANGUAGE
#define BCSR0		BCSR_BASE_ADRS 		/* Register 0 */
#define BCSR1		BCSR_BASE_ADRS + 0x04	/* Register 1 */
#define BCSR2		BCSR_BASE_ADRS + 0x08	/* Register 2 */
#define BCSR3		BCSR_BASE_ADRS + 0x0c	/* Register 3 */
#define	BCSR2_BREVN_MASK	0x00000f00	/* Board revision number */
#else
#define BCSR0		((char *) (BCSR_BASE_ADRS))	     /* Register 0 */
#define BCSR1		((UINT32 *) (BCSR_BASE_ADRS + 0x04)) /* Register 1 */
#define BCSR2		((UINT32 *) (BCSR_BASE_ADRS + 0x08)) /* Register 2 */
#define BCSR3		((UINT32 *) (BCSR_BASE_ADRS + 0x0c)) /* Register 3 */
#endif	/* _ASMLANGUAGE */

#ifdef BOARD_REV_PILOT

/* BCSR0 bit definition (active at low level when _L) */
/*
0 1 2 3 4 5 6 7 8-31
| | | | | | | |  `-- 0x00800000 through 0x00000001   reserved
| | | | | | | `----- 0x01000000 BCSR0_SIG_LED1_L     Signal LED 1 (red)
| | | | | | `------- 0x02000000 BCSR0_SIG_LED0_L     Signal LED 0 (green)
| | | | | `--------- 0x04000000 BCSR0_L2_CLEAR_L     L2 Cache Clear
| | | | `----------- 0x08000000 BCSR0_L2_LOCK_L      L2 Cache Lock
| | | `------------- 0x10000000 BCSR0_L2_FLUSH_L     L2 Cache Flush
| | `--------------- 0x20000000 BCSR0_L2_INHIBIT_L   L2 Cache Inhibit
| `----------------- 0x40000000 BCSR0_L2_DIMM_SIZE_L L2 SDRAM DIMM Size
`------------------- 0x80000000 BCSR0_L2_PBI_L       L2 Page Based Interleave

*/

#define BCSR0_SIG_LED1_L	0x01000000	/* LED 1 */
#define BCSR0_LED_RED		BCSR0_SIG_LED1_L
#define BCSR0_SIG_LED0_L	0x02000000	/* LED 0 */
#define BCSR0_LED_GREEN		BCSR0_SIG_LED0_L
#define BCSR0_LED_ON		0x1
#define BCSR0_LED_OFF		0x0
#define BCSR0_L2_CLEAR_L	0x04000000	/* L2 Cache Clear */
#define BCSR0_L2_LOCK_L		0x08000000	/* L2 Cache Lock */
#define BCSR0_L2_FLUSH_L	0x10000000	/* L2 Cache Flush */
#define BCSR0_L2_INHIBIT_L	0x20000000	/* L2 Cache Inhibit */
#define BCSR0_L2_DIMM_SIZE_L	0x40000000	/* L2 SDRAM DIMM Size */
#define BCSR0_L2_PBI_L	        0x80000000	/* L2 Page Based Interleave */

/* BCSR1 bit definition (active at low level when _L) */
/*
0 1 2 3 4 5 6 7 8-31
| | | | | | | |  `-- 0x00800000 through 0x00000001   reserved
| | | | | | | `----- 0x01000000 BCSR1_RS232EN_2_L  RS232 Port 2 Enable
| | | | | | `------- 0x02000000 BCSR1_RS232EN_1_L  RS232 Port 1 Enable
| | | | | `--------- 0x04000000 BCSR1_FETH_RST_L   Fast Ethernet Port Reset
| | | | `----------- 0x08000000 BCSR1_FETH_IEN_L   Fast Ethernet Port Initial
| | | |                                              Enable
| | | `------------- 0x10000000 BCSR1_ATM_RST_L    ATM Port Reset
| | `--------------- 0x20000000 BCSR1_ATM_EN_L     ATM Port Enable
```----------------- 0x40000000 thru 0x80000000  reserved
 */

#define BCSR1_RS232EN_2_L	0x01000000	/* RS232 port 2 enable */
#define BCSR1_RS232EN_1_L	0x02000000	/* RS232 port 1 enable */
#define BCSR1_FETH_RST_L	0x04000000	/* Fast Ethernet Port Reset */
#define BCSR1_FETH_IEN_L	0x08000000   /* Fast Enet Port Initial Enable */
#define BCSR1_ATM_RST_L		0x10000000  	/* ATM Port Reset */
#define BCSR1_ATM_EN_L		0x20000000  	/* ATM Port Enable */

/* BCSR2 bit definition */

#define BCSR2_TOOL_STAT_MASK		0xff000000	/* Tool Status mask */
#define BCSR2_TOOL_REV_MASK		0x00f00000	/* Tool Revision mask */
#define BCSR2_EXT_TOOL_ID_MASK 		0x000f0000	/* External Tool ID */
#define BCSR2_SWOPT_01_MASK		0x0000c000	/* DS3[1:2] mask */
#define BCSR2_L2CSIZE_MASK		0x00003000	/* L2 Cache Size mask */
#define BCSR2_BREVN_MASK		0x00000f00	/* Board rev number */
#define BCSR2_SWOPT_2_MASK	  	0x00000080	/* DS3[3] mask */
#define BCSR2_FLASH_PD_75_MASK 		0x00000070	/* Flash Presence 
							     Detect[7:5] mask */
#define BCSR2_FLASH_PD_41_MASK 		0x0000007f	/* Flash Presence 
							     Detect[4:1] mask */
#else /* BOARD_REV_PILOT */		

/* otherwise board revision is ENG */

/* BCSR0 bit definition (active at low level when _L) */
/*
0-25 26 27 28 29 30 31 
 |    |  |  |  |  |  `- 0x00000001 BCSR0_SIG_LED1_L   Signal LED 1 (red)
 |    |  |  |  |  `---- 0x00000002 BCSR0_SIG_LED0_L   Signal LED 0 (green)
 |    |  |  |  `------- 0x00000004 BCSR0_L2_CLEAR_L   L2 Cache Clear
 |    |  |  `---------- 0x00000008 BCSR0_L2_LOCK_L    L2 Cache Lock
 |    |  `------------- 0x00000010 BCSR0_L2_FLUSH_L   L2 Cache Flush
 |    `---------------- 0x00000020 BCSR0_L2_INHIBIT_L L2 Cache Inhibit
 `--------------------- 0x00000040 thru 0x80000000    reserved
 */

#define BCSR0_SIG_LED1_L	0x00000001	/* LED 1 */
#define BCSR0_LED_RED		BCSR0_SIG_LED1_L
#define BCSR0_SIG_LED0_L	0x00000002	/* LED 0 */
#define BCSR0_LED_GREEN		BCSR0_SIG_LED0_L
#define BCSR0_LED_ON		0x1
#define BCSR0_LED_OFF		0x0
#define BCSR0_L2_CLEAR_L	0x00000004	/* L2 Cache Clear */
#define BCSR0_L2_LOCK_L		0x00000008	/* L2 Cache Lock */
#define BCSR0_L2_FLUSH_L	0x00000010	/* L2 Cache Flush */
#define BCSR0_L2_INHIBIT_L	0x00000020	/* L2 Cache Inhibit */

/* BCSR1 bit definition (active at low level when _L) */
/*
0-25 26 27 28 29 30 31 
 |    |  |  |  |  |  `- 0x00000001 BCSR1_RS232EN_2_L  RS232 Port 2 Enable
 |    |  |  |  |  `---- 0x00000002 BCSR1_RS232EN_1_L  RS232 Port 1 Enable
 |    |  |  |  `------- 0x00000004 BCSR1_FETH_RST_L   Fast Ethernet Port Reset
 |    |  |  `---------- 0x00000008 BCSR1_FETH_IEN_L   Fast Ethernet Port Initial
 |    |  |                                              Enable
 |    |  `------------- 0x00000010 BCSR1_ATM_RST_L    ATM Port Reset
 |    `---------------- 0x00000020 BCSR1_ATM_EN_L     ATM Port Enable
 `--------------------- 0x00000040 thru 0x80000000  reserved
 */

#define BCSR1_RS232EN_2_L	0x00000001	/* RS232 port 2 enable */
#define BCSR1_RS232EN_1_L	0x00000002	/* RS232 port 1 enable */
#define BCSR1_FETH_RST_L	0x00000004	/* Fast Ethernet Port Reset */
#define BCSR1_FETH_IEN_L	0x00000008   /* Fast Enet Port Initial Enable */
#define BCSR1_ATM_RST_L		0x00000010  	/* ATM Port Reset */
#define BCSR1_ATM_EN_L		0x00000020  	/* ATM Port Enable */

/* BCSR2 bit definition */

#define BCSR2_BREVN			0x00000f00	/* Board rev number */

#define BCSR2_FLASH_PD_2MEG_SIMM	0x80000000	/* Flash presence 2 M */
#define BCSR2_FLASH_PD_4MEG_SIMM	0x70000000	/* Flash presence 4 M */
#define BCSR2_FLASH_PD_8MEG_SIMM	0x60000000	/* Flash presence 8 M */
#define BCSR2_DRAM_EDO_L		0x00000000	/* Dram is EDO */
#define BCSR2_DRAM_NO_EDO_L		0x08000000	/* Dram is not EDO */
#define BCSR2_DRAM_PD_4MEG_SIMM		0x00000000	/* Dram presence  4 M */
#define BCSR2_DRAM_PD_32MEG_SIMM	0x00800000	/* Dram presence 32 M */
#define BCSR2_DRAM_PD_16MEG_SIMM	0x01000000	/* Dram presence 16 M */
#define BCSR2_DRAM_PD_8MEG_SIMM		0x01800000	/* Dram presence  8 M */
#define BCSR2_DRAM_PD_SIZE_MASK		0x01800000	/* Dram size mask */
#define BCSR2_DRAM_PD_70NS_SIMM		0x04000000	/* Dram presence 70ns */
#define BCSR2_DRAM_PD_60NS_SIMM		0x06000000	/* Dram presence 60ns */
#define BCSR2_DRAM_PD_SPEED_MASK	0x06000000	/* Dram spreed mask */

/* BCSR3 bit definition */

#define BCSR3_CTR_REG_PROT_EN		0x08000000	/* Ctrl reg Protect */
#define BCSR3_FLASH_PD			0x00700000	/* Flash Presence det */

#define BCSR3_DBID_MASK                 0x3f000000  /* FADS daughter board id */
#define BCSR3_ADS_MASK                  0x00000000  /* Mask for 8xxADS board */
#define BCSR3_813DB_MASK                0x01000000  /* Mask for MPC813 db */
#define BCSR3_821DB_MASK                0x02000000  /* Mask for MPC821 db */
#define BCSR3_823DB_MASK                0x03000000  /* Mask for MPC823 db */
#define BCSR3_801DB_MASK                0x20000000  /* Mask for MPC801 db */
#define BCSR3_850DB_MASK                0x21000000  /* Mask for MPC850 db */
#define BCSR3_860DB_MASK                0x22000000  /* Mask for MPC860 db */
#define BCSR3_860SARDB_MASK             0x23000000  /* Mask for MPC860SAR db */
#define BCSR3_860TDB_MASK               0x24000000  /* Mask for MPC860T db */
#define BCSR3_8260DB_MASK               0xAAAAAAAA  /* Mask for MPC8260 db */

/* BCSR4 bit definition */

#define BCSR4_ETHLOOP                   0x80000000  /* Ethernet Loop Back */
#define BCSR4_TFPLDL_L                  0x40000000  /* TP Full-Duplex */
#define BCSR4_TPSQEL_L                  0x20000000  /* Signal Quality Test */
#define BCSR4_SIGNAL_LAMP_L             0x20000000  /* Signal Lamp Enable Low*/
#define BCSR4_MODEM_EN_L                0x00100000  /* Modem Enable on PPC823 */
#define BCSR4_DATA_VOICE_L              0x00080000  /* */

#endif /* BOARD_REV_PILOT */		

#define BCSR1_RESET_VAL		(BCSR1_RS232EN_2_L    | BCSR1_RS232EN_1_L | \
				 BCSR1_FETH_RST_L     | BCSR1_FETH_IEN_L  | \
				 BCSR1_ATM_RST_L      | BCSR1_ATM_EN_L)

/* CPU type in the PVR */

#define CPU_TYPE_8260			0xAAAA		/* value for PPC8260 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */

/* 
 * Maximum number of SCC channels to configure as SIOs. Note that this 
 * assumes sequential usage of SCCs.
*/
#define MAX_SCC_SIO_CHANS 2

#ifdef __cplusplus
    }
#endif


#endif /* INCads8260h */