target.nr

WINDRIVER ADS8260 BSP

.SS "Shared Memory"
NA

.SS "Interrupts"
.LP
The following table describes the relationship between the interrupt
number, interrupt vector, and the interrupt bit position in the SIU
Interrupt Mask Register (SIMR_H and SIMR_L). Also described is the
mask to use to enable all interrupts of a higher priority. See m8260Int.c
for usage.
.TS 
center;
c c c c c s c
c c c c c s c
c c c c c c c
nw(.3i) n n n n n l.
Default				Mask to Enable
Interrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	Interrupt
Priority	Number	Vector	Mask	SIMR_H	SIMR_L	Source
						HIGHEST PRIORITY
1	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
2	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
3	17	0x11	H 0x00000002	0000_0004	0000_0000	PIT
4	reserved
5	19	0x13	H 0x00004000	0000_0006	0000_0000	IRQ1
6	27	0x20	L 0x80000000	0000_4006	0000_0000	FCC1
7	28	0x21	L 0x40000000	0000_4006	8000_0000	FCC2
8	29	0x22	L 0x20000000	0000_4006	C000_0000	FCC3
9	inactive
10	unused
11	31	0x24	L 0x08000000	0000_4006	E000_0000	MCC1
12	32	0x25	L 0x04000000	0000_4006	E800_0000	MCC2
13	inactive
14	inactive
15	20	0x13	H 0x00002000	0000_4006	EC00_0000	IRQ2
16	21	0x14	H 0x00001000	0000_6006	EC00_0000	IRQ3
17	22	0x15	H 0x00000800	0000_7006	EC00_0000	IRQ4
18	23	0x16	H 0x00000400	0000_7806	EC00_0000	IRQ5
19	unused
20	35	0x28	L 0x00800000	0000_7C06	EC00_0000	SCC1
21	36	0x29	L 0x00400000	0000_7C06	EC80_0000	SCC2
22	37	0x2A	L 0x00200000	0000_7C06	ECC0_0000	SCC3
23	38	0x2B	L 0x00100000	0000_7C06	ECE0_0000	SCC4
24	inactive
25	inactive
26	inactive
27	inactive
28	unused
29	40	0x30	H 0x00010000	0000_7C06	ECF0_0000	PC15
30	12	0x0C	L 0x00000010	0001_7C06	ECF0_0000	Timer 1
31	41	0x31	H 0x00020000	0001_7C06	ECF0_0010	PC14
32	unused
33	42	0x32	H 0x00040000	0003_7C06	ECF0_0010	PC13
34	10	0x0A	L 0x00000040	0007_7C06	ECF0_0010	SDMA Bus Error
35	6	0x06	L 0x00000400	0007_7C06	ECF0_0050	IDMA1
36	unused
37	43	0x33	H 0x00080000	0007_7C06	ECF0_0450	PC12
38	44	0x34	H 0x00100000	000F_7C06	ECF0_0450	PC11
39	7	0x07	L 0x00000200	001F_7C06	ECF0_0450	IDMA2
40	13	0x0D	L 0x00000008	001F_7C06	ECF0_0650	Timer 2
41	45	0x35	H 0x00200000	001F_7C06	ECF0_0658	PC10
42	unused
43	unused
44	3	0x03	L 0x00002000	003F_7C06	ECF0_0658	RISC Timer Table
45	1	0x01	L 0x00008000	003F_7C06	ECF0_2658	I2C
46	unused
47	46	0x36	H 0x00400000	003F_7C06	ECF0_A658	PC9
48	47	0x37	H 0x00800000	007F_7C06	ECF0_A658	PC8
49	24	0x18	H 0x00000200	00FF_7C06	ECF0_A658	IRQ6
50	8	0x08	L 0x00000100	00FF_7E06	ECF0_A658	IDMA3
51	25	0x19	H 0x00000100	00FF_7E06	ECF0_A758	IRQ7
52	14	0x0E	L 0x00000004	00FF_7F06	ECF0_A758	Timer 3
53	unused
54	unused
55	48	0x38	H 0x01000000	00FF_7F06	ECF0_A75C	PC7
56	49	0x39	H 0x02000000	01FF_7F06	ECF0_A75C	PC6
57	50	0x3A	H 0x04000000	03FF_7F06	ECF0_A75C	PC5
58	15	0x0F	L 0x00000002	07FF_7F06	ECF0_A75C	Timer 4
59	unused
60	51	0x3B	H 0x08000000	07FF_7F06	ECF0_A75E	PC4
61	unused
62	9	0x09	L 0x00000080	0FFF_7F06	ECF0_A75E	IDMA4
63	2	0x02	L 0x00004000	0FFF_7F06	ECF0_A7DE	SPI
64	52	0x3C	H 0x10000000	0FFF_7F06	ECF0_E7DE	PC3
65	53	0x3D	H 0x20000000	1FFF_7F06	ECF0_E7DE	PC2
66	4	0x04	L 0x00001000	3FFF_7F06	ECF0_E7DE	SMC1
67	unused
68	5	0x05	L 0x00000800	3FFF_7F06	ECF0_F7DE	SMC2
69	54	0x3E	H 0x40000000	3FFF_7F06	ECF0_FFDE	PC1
70	55	0x3F	H 0x80000000	7FFF_7F06	ECF0_FFDE	PC0
71	unused
72	unused
73	reserved
						LOWEST PRIORITY

.TE

.SS "Serial Configuration"
SCC1 and SCC2 are configured as UART devices with 8 data bits, 1 stop
bit, hardware handshaking, and parity disabled. 

.SS "SCSI Configuration"
There is no SCSI interface on this board.

.SS "Network Configuration"
FCC2 is configured as an Ethernet port

.SS "VME Access"
NA

.SS "PCI Access"
There is no PCI interface on this board.

.SS "Boot Devices"
motFcc

.SS "Boot Methods"
Ethernet

Load image via Macraigor Raven and invoke via "OCD Commander"

.SS "ROM Considerations for PILOT board revision"
The actual size of Flash memory on this board is 8MB (optionally
16MB or 32MB) starting at (0xffffffff - FLASH_SIZE). 

The system exception vector table is placed at 0xfff00000,
so boot-up code has to be programmed at this location.

The BSP was tested with both compressed and uncompressed boot roms
programmed at this location. If there is not enough space for the
bootrom image or a vxWorks standalone image is required to be in
ROM, this can be achieved by placing a stub that jumps to start of
flash memory. This requires either a compiler which can
provide 2 text segments or manually programming the stub and the
main image at different locations without overwriting each other.


.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information that the user needs
to know about the BSP.

.SS "Delivered Objects"

.SS "Make Targets"
Bootrom_uncmp, vxWorks and vxWorks.st are delivered. All other
make targets are untested. For PILOT revision of board, bootrom
(compressed) is also tested.

.SS "Special Routines"
None

.SS "Serial Connections"
Most VxWorks BSPs do not use hardware handshaking in the serial
interface, and thus a simple 3 wire connection is commonly used.  The
MPC8260 ADS BSP does use hardware handshaking and this requires 
a full 8 pin interface. Standard molded RS-232 cables have been shown
to work, possibly requiring a null modem adapter.

See also "Known Problems" below.

.SS "Ethernet Address"
The MPC8260 ADS boards do not have a unique Ethernet hardware
address assigned to each board.  A unique address is absolutely necessary if
the user wishes to connect the board to a network.  Thus, the user
must provide a suitable 6 byte Ethernet address for each board used
on a network.  The address is programmed by changing the sysFccEnetAddr
character array in the file sysLib.c.  The first three bytes (0x08, 0x00, 0x3e)
are a Motorola-specific prefix that should be kept as-is.  The user must
change the last three bytes from 0x03, 0x02, 0x01 to three unique bytes
(i.e., bytes not used by any other Motorola Ethernet connection on your net).
Check with your system administrator if you do not know this information.

.SS "Documentation Errata"
Note that in the Motorola MPC8260 PowerQUICC II ADS User's Manual
the size of the MPC8260's Internal MAP is incorrectly stated.
it is stated correctly in the Motorola MPC8260 PowerQUICC II User's 
Manual as 128K bytes.

.SS "Known Problems"
Serial driver transmitter hangs if receiver is hit too rapidly; however
receiver continues to function.

.SS "Initialization Values"

The VxWorks bootrom completely initializes the board. On the other
hand, VxWorks does not reinitialize many registers.  
Thus, when the VxWorks image is loaded via the Macraigor Raven and vbug,
most values are initialized by the debugger and not by VxWorks.
For a list of initialized values, refer to the 
"VBUG PowerQUICC II Debugger"

.bp
.SS "Tested Configuration"

The MPC8260 chip, the MPC8260 ADS, and the host-based software
as purchased might differ from the ones used to develop this bsp. 
Thus, we document the configuration that was used to develop the BSP:


.LP
Board Markings:
.CS
MPC8260 ADS
REV. PILOT  (for PILOT revision of board)
.CE
.LP
CPU Chip Markings:
.CS
PPC8260ZU
2J24M CREAA9927 HKG (for PILOT rev)
.CE
.LP
SYSCLK oscillator: 
.CS
40 MHz 
.CE
.LP
DIP Switches for PILOT rev:
.IP
PON. RST. CONF. (DS1):
.TS
center;
l l
l l.
Label	Position
_
FLASH/BCSR	Off
MODCKH 0	On
MODCKH 1	Off
MODCKH 2	On
MODCKH 3	Off
MODCK  1	Off
MODCK  2	Off
MODCK  3	Off
.TE
.LP

.IP
SDRAM CONF. ADD. (DS2) for PILOT rev:
.TS
center;
l l
l l.
Label	Position
_
SA2	Off
SA1	Off
SA0	Off
RESERVED	Off
.TE
.LP


.SS "SDRAM Interleave Modes"
According to the latest manual, bit 0 of PSDMR is "PBI", Page Based
Interleave.
This is true for silicon rev A, which is not yet available. 
For the silicon that is currently available,
this bit is reserved and should be 0, as the sample
initialization code indicates.

Silicon before Rev A supports only Bank Based Interleave. Page
Based Interleave will be available only on silicon rev A and beyond.

.SS "SYSCLK Frequency"
Most Motorola sample code and documentation refers to a default system clock
frequency of 66 MHz; However, problems occur at this frequency, and thus
the ADS is normally delivered with a 40 MHz oscillator.

.SH "BOARD LAYOUT"
The diagram below shows jumpers and connectors relevant to 
VxWorks configuration for PILOT revisions of the board.

.bS
___________________________________________________________________________
|  RS-232 1 (upper)    P5                                                 |
|  RS-232 2 (lower)    COP-JTAG
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
| P2 - Ethernet                                                           |
|                                                                   P19   |
|                                                                  Power  |
|                            -------------                        ________|
|     P4 - CPM expansion     |            |  P16 - SYS expansion  |
|____________________________|            |_______________________|
.bE
    Key: 
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration," 
.pG "Architecture Appendix"

.SH "BIBLIOGRAPHY"

.iB "MPC8260 ADS User's Manual"
.iB "MPC8260ADS User's Manual, for PILOT revision bd, 11/1999"
.iB "PowerQUICC II User's Manual, rev. 0"
.iB "MPC8260 PowerQUICC II User's Manual Errata, rev. 0"
.iB "MPC8260 Design Checklist"
.iB "PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD"
.iB "MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD"
.iB "VBUG PowerQUICC II Debugger"

.SH "WEB RESOURCES"

Much of the Motorola documentation can be found on line. The following
URL was correct at the time of writing; however, Motorola may move these
pages without notifying Wind River Systems.

http://www.mot.com/SPS/RISC/netcomm/prod/eppc/MPC8260.html

Contains the following:

    MPC8260 Product Briefs
    MPC8260 User's Manuals
    MPC8260 Hardware Specifications
    MPC8260 Errata
    MPC8260 Third Party Support
    MPC8260 Training Materials

http://www.mot.com/netcomm

Contains the following:

    MPC8260ADS User's Manual, for PILOT revision bd, 11/1999

http://www.mot.com/SPS/RISC/netcomm/docs/pubs/index.html

Contains the following:

    MPC8260 PowerQUICC II User's Manual, rev. 0
    MPC8260 PowerQUICC II User's Manual Errata, rev. 0
    MPC8260 Design Checklist