syslib.c

INTEL IXP425的VXWORKS BSP

/* sysLib.c - IXP425 ixdp425 Emulator Board Specific routines */

/* Copyright 2002 Wind River Systems, Inc. */

#include "copyright_wrs.h"

/*
modification history
--------------------
01m,04apr03,m_h  Misc support for ixeth init
01l,23oct02,jb  Adding CS1 setup
01k,22oct02,jb  Changing to correct reserved memory name
01j,07oct02,jb  Fix print statement
01i,07oct02,jb  Remove IP address size change
01h,23sep02,jb  Changing sysPhysMemDesc to use LOCAL_MEM_SIZE
01g,18sep02,jb  Rename appinit
01f,19aug02,jb  Force redefines for ixe driver
01e,15aug02,jb  Enabling ixp425IfConfig
01d,01aug02,jb  Fixing sysToMonitor with ixe
01c,26jun02,jb  Adding ixp425 End support
01b,13jun02,jb  Fixing sysToMonitor
01a,05jun02,jb  initial version... from Peter
*/

/*
DESCRIPTION
This library provides board-specific routines.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "stdio.h"
#include "usrLib.h"
#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "inetLib.h"
#include "fioLib.h"
#include "rebootLib.h"
#include "ctype.h"
#include "logLib.h"
#include "errnoLib.h"

#include "bootLib.h"
#include "vme.h"
#include "in.h"
#include "memLib.h"
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "arch/arm/cacheArmLib.h"
#include "private/vmLibP.h"

#include "debugutils.h"

#if defined(INCLUDE_IXETHACCEND)
#include "IxQMgr.h"
#endif /*defined(INCLUDE_IXETHACCEND)*/

/* Source Drivers */
#ifdef INCLUDE_FLASH
    #include "mem/flashMem.c"
    #ifdef USE_FLASH_STORAGE
        #include "mem/nvRamToFlash.c"
    #endif
#endif /* INCLUDE_FLASH */

#ifdef INCLUDE_EEPROM
    #include "ixp425I2c.c"
    #include "ixp425Eeprom.c"
#endif /* INCLUDE_EEPROM */

/* No non-volatile storage available */
#if !defined(INCLUDE_FLASH) && !defined(INCLUDE_EEPROM)
    #include "mem/nullNvRam.c"
#endif

#include "ixp425Gpio.c"

#ifdef INCLUDE_PCI
    #include "ixp425Pci.c"
    #include "ixp425PciIntLib.c"
    #include "ixp425PciConfigLib.c"
    #include "ixp425PciConfigShow.c"
    #ifdef INCLUDE_PCI_DMA
        #include "ixp425PciDma.c"
    #endif
#endif


#if defined(INCLUDE_END)
#include "end.h"
#if defined(INCLUDE_FEI82557END)
    #include "sysEnd.c"
STATUS sysLanPciInit (void);
#ifdef IXDP_FEIEND_USE_NVRAM_IP
#if defined(IXDP_FEI557_IP0_DEFAULT) && defined(IXDP_FEI557_IP1_DEFAULT) && defined(IXDP_FEI557_IP2_DEFAULT) && defined(IXDP_FEI557_IP3_DEFAULT)
LOCAL char *defaultfeiInetAddr[IXP425_MAX_FEI_DEVS] =
    {
    IXDP_FEI557_IP0_DEFAULT,
    IXDP_FEI557_IP1_DEFAULT,
    IXDP_FEI557_IP2_DEFAULT,
    IXDP_FEI557_IP3_DEFAULT,
    };
#endif /* All DEFAULTS */
#endif /* IXDP_FEIEND_USE_NVRAM_IP */
#endif /* INCLUDE_FEI82557END */

#include "IxEthAcc.h" /* Always include this */
#include "IxNpeDl.h"  /* Always include this */
#include "IxNpeMh.h"  /* Always include this */
#include "IxQMgr.h"   /* Always include this */
#if defined(INCLUDE_IXETHACCEND)
STATUS ixdp425EthEndMuxInit(void);
STATUS ixdp425EthEndStartUp(void);
#endif /* INCLUDE_IXETHACCEND */

IMPORT int  ipAttach ();
#endif /* INCLUDE_END */

#include "ixdp425.h"


/*
 * Ixp425 Interrupt Controller Board Specifics. 
 */

/*
 * This array maps interrupt levels to mask patterns.  The interrupt level
 * is the index, the data is the mask value.  A mask bit enables one
 * level.  The mask value is 'and'd with the ixp425IntLvlEnabled value
 * before writing to the chip.
 */

#include "ixp425IntrCtl.h"

LOCAL UINT32 ixp425IntLvlMask [IXP425_INT_NUM_LEVELS + 1] = /* int lvl mask */
    {
    0x0000,                             /* level 0, all disabled */
    0x00000001, 0x00000003, 0x00000007, 0x0000000f,
    0x0000001f, 0x0000003f, 0x0000007f, 0x000000ff,
    0x000001ff, 0x000003ff, 0x000007ff, 0x00000fff,
    0x00001fff, 0x00003fff, 0x00007fff, 0x0000ffff,
    0x0001ffff, 0x0003ffff, 0x0007ffff, 0x000fffff,
    0x001fffff, 0x003fffff, 0x007fffff, 0x00ffffff,
    0x01ffffff, 0x03ffffff, 0x07ffffff, 0x0fffffff,
    0x1fffffff, 0x3fffffff, 0x7fffffff, 0xffffffff,
    /* level 32 all enabled */
    };

#if IXP425_INT_NUM_LEVELS != 32
    #error ixp425IntLvlMask is wrong size for number of levels
#endif  


#include "ixp425IntrCtl.c"
#include "ixp425Timer.c"
#include "sysSerial.c"


/* enable interrupts/fiqs on XScale */
extern void sysEnableIRQMasks ();
extern void sysToMonSwitchFlashRam();

/* retrieve auto-sized memory */
extern UINT32 sysPhysMemSize ();

/* find a device using its string name */
extern END_OBJ* endFindByName (char* pName, int unit);
extern int  sysMacGet();


/* externals */
IMPORT char end;                /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */
IMPORT void sysIntStackSplit (char *, long);
IMPORT void printfxu(char *ptr);

/* globals */
/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC or INCLUDE_MMU_FULL are
 * defined.
 *
 * The following are not the smallest areas that could be allocated for a
 * working system.  If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

#ifdef INCLUDE_MMU

void *mmuPhysToVirt(void *physicalAddress);
void *mmuVirtToPhys(void *virtualAddress);

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    { /* Init Boot Code From Flash Bank 1 */
        (void *) IXP425_SDRAM_BASE,       /* virtual address */
        (void *) IXP425_SDRAM_BASE,       /* physical address */
        LOCAL_MEM_SIZE,                  /* length, then initial state: */  /* Entire SDRAM space */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID  | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE | VM_STATE_BUFFERABLE
    },

    { /* PCI Config space   */
        (void *) IXP425_PCI_CONFIG_BASE ,                 /* virtual address */
        (void *) IXP425_PCI_CONFIG_BASE,                  /* physical address */
        SZ_4K ,                                           /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Expansion bus Register Block  */
        (void *) IXP425_EXP_CONFIG_BASE ,             /* virtual address */
        (void *) IXP425_EXP_CONFIG_BASE,              /* physical address */
        SZ_4K,                        /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID  | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Peripheral Register Block  */
        (void *) IXP425_PERIPHERAL_BASE ,             /* virtual address */
        (void *) IXP425_PERIPHERAL_BASE,              /* physical address */
        SZ_64K,                       /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID  | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* QMgr Register Block  */
        (void *) IXP425_QMGR_BASE ,           /* virtual address */
        (void *) IXP425_QMGR_BASE,            /* physical address */
        SZ_16K,                       /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID  | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* SDRAM Config register space   */
        (void *) IXP425_SDRAM_CONFIG_BASE ,                 /* virtual address */
        (void *) IXP425_SDRAM_CONFIG_BASE,                  /* physical address */
        SZ_4K ,                                            /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },


#ifdef INCLUDE_FAST_DRAM
    { /* data cache fast dram option */
      /* No external memory request is made, which means software can map any
       * unallocated area of memory as data RAM. However, the line-allocate operation
       * does validate the target address with the MMU, so system software must ensure
       * that the memory has a valid descriptor in the page table.
       */
        (void *) FD_ORIGIN,               /* virtual address */
        (void *) FD_ORIGIN,               /* physical address */
        FD_MAX_SIZE,                  /* length (plus rounded-up), then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID  | VM_STATE_WRITABLE  | VM_STATE_CACHEABLE
    },
#endif

    { /* Flash Bank CS0 - Relocated base */
        (void *) IXP425_EXPANSION_BUS_BASE2,          /* virtual address */
        (void *) IXP425_EXPANSION_BUS_BASE2,          /* physical address */
        SZ_16M,                   /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 1 - CS1  */
        (void *) IXP425_EXPANSION_BUS_CS1_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS1_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 2 - CS2  */
        (void *) IXP425_EXPANSION_BUS_CS2_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS2_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 3 - CS3  */
        (void *) IXP425_EXPANSION_BUS_CS3_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS3_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 4 - CS4  */
        (void *) IXP425_EXPANSION_BUS_CS4_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS4_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 5 - CS5  */
        (void *) IXP425_EXPANSION_BUS_CS5_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS5_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 6 - CS6  */
        (void *) IXP425_EXPANSION_BUS_CS6_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS6_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

    { /* Chip Select 7 - CS7  */
        (void *) IXP425_EXPANSION_BUS_CS7_BASE,              /* virtual address */
        (void *) IXP425_EXPANSION_BUS_CS7_BASE,              /* physical address */
        SZ_16M,                               /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },

#ifdef  INCLUDE_PCI
    { /* PCI Memory,IO,Config   */
        (void *) IXP425_PCI_BASE,              /* virtual address */
        (void *) IXP425_PCI_BASE,              /* physical address */
        IXP425_PCI_SP_SIZE,                    /* length, then initial state: */
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_BUFFERABLE_NOT
    },
#endif

    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /*  INCLUDE_MMU */

int sysCpu       = CPU;     /* system CPU type */
char *  sysBootLine = BOOT_LINE_ADRS;   /* address of boot line */
char    sysBootHost [BOOT_FIELD_LEN];   /* name of host from which we booted */
char    sysBootFile [BOOT_FIELD_LEN];   /* name of file from which we booted */
#if defined(INCLUDE_IXETHACCEND)
static int loadIxe = 0;		/* whether or not to load ixe END driver */
#endif /*INCLUDE_IXETHACCEND*/

int sysFlags;           /* boot flags */
int sysProcNum = 0;         /* processor number of this CPU */

/* Area used to flush D-cache */
UINT32 sysCacheFlushReadArea[D_CACHE_SIZE/sizeof(UINT32)];

/* Area used to flush mini-cache */
UINT32 sysMinicacheFlushReadArea[MINI_CACHE_SIZE/sizeof(UINT32)];

char    *sysExcMsg   = EXC_MSG_ADRS;    /* catastrophic message area */

/* forward LOCAL function declarations */
/* forward declarations */
char *  sysPhysMemTop (void);