sysend.c.bak

INTEL IXP425的VXWORKS BSP

/* sysEnd.c - System Enhanced network interface support library */

/* Copyright 2002 Wind River Systems, Inc. */

#include "copyright_wrs.h"

/*
modification history
--------------------
01f,04apr03,m_h  Spelling RDFS becomes RFDS
01e,05sep02,jb3  Merge in changes from w/ t2.1 ongiong development
01e,01aug02,jb  Removing Dec device support
01d,30jul02,jb  Removing debug code
01c,27jun02,jb  Fix warnings
01b,18jun02,jb  Changing size calculation to allow veloce driver to work
01a,05jun02,jb  initial version...
*/

/*
DESCRIPTION
This file contains the board-specific routines for Ethernet adapter
initialisation of Intel Pro 100+ based adapters.

NOTE
At the time of writing, this module has only been tested with the following
Ethernet cards:
    82559 controller: Intel PRO/100+ Management Adapter
                      Intel InBusiness 10/100 PCI Network Adapter

Refer to the BSP reference entry for any eventual limitations or
problems related to the BSP.


SEE ALSO: ifLib,
.I "Intel 10/100 MBit Ethernet Family Software technical Reference Manual."
*/

#include "vxWorks.h"
#include "config.h"
#include "cacheLib.h"

#include "stdio.h"

#ifdef INCLUDE_END
#include "end.h"
#include "netinet/if_ether.h"

#include "fei82557End.h"
#include "ixp425Pci.h"


#ifdef END_DEBUG
#undef LOCAL
#define LOCAL
#endif

/* defines */


#define CSR_BASE_MSK	0x7f		/* Mask Base Address Register */
#define	END_LD_STR_SIZE	80

/* PCI memory base address register configuration mode */

#define FORCE		0x00	/* overwrite membase address register */
#define AUTO		0x01	/* read membase address register */

/*
 * Need to use automatic configuration mode using the resource assigning in
 * pciAssignResources().
 */

#define PCI_REG_MOD	AUTO	/* define the register configuration mode */

#define TYPE_ALLOC	1000

    /*Everything tested & works fine with a delay of 1, but set to 3 in 
      order to eliminate the possibility of any timing issues with temp. increase etc*/
#define PCI_CONFIG_DELAY 3 
     

/*
 * FEI cards in range 1001 -> 2000
 */

#define FEI_START	TYPE_ALLOC + 1

#define PRO100B		FEI_START	/* Intel EtherExpress PRO-100B PCI */
#define INBUSINESS	FEI_START + 1	/* Intel InBusiness 10/100 PCI */

#define XX82559ER 	FEI_START + 100	/* Arbitrary card with 82559ER */

#define	BOARD_TYPE_NB			(NELEMENTS(boardResources))


#ifdef INCLUDE_FEI82557END

/* the following two are tunable parameters which specify the
   number of transmit and receive buffers to be allocated for
   use by an fei (82559) driver. These must never be set below 2,
   otherwise the driver will assume a default of 32, and our
   calculations of how much memory to allocate for the 
   driver will be in error*/
#define FEI_N_RFDS         32
#define FEI_N_TFDS         32
/*
 * FEI_RFD_MULTIPLIER is the multiplier that is applied to the number of RFDs requested
 * to determine the number of "spares" available for loaning to the network
 * stack. This value (4) was taken from the fei driver source code (its not
 * available in the header, so if this changes in future versions of the driver
 * this will break - if it is increased the driver will complain that we have not
 * given it enough memory, if it is decreased everything will work but we will be 
 * wasting SDRAM.
 */
#define FEI_RFD_MULTIPLIER 4
#define FEI_N_RFD_LOAN     (FEI_N_RFDS * FEI_RFD_MULTIPLIER)
/*
 * Again  FEI_CL_OVERHEAD has been taken from the fei source code (not specified in header),
 * so the caveats for the FEI_RFD_MULTIPLIER apply here too
 */
#define FEI_CL_OVERHEAD    4 /* prepended cluster header */

#define FEI_CL_RFD_SIZE    (RFD_SIZE + FEI_CL_OVERHEAD)
#define FEI_CFD_SIZE       CFD_SIZE
/*This calculation is taken from the fei driver source, again, if this changes, the driver will 
  either complain that it has not been allocated enough memory, or will work fine but we will
  be wasting SDRAM*/
#define FEI_TOTAL_SIZE     ((FEI_N_RFDS * FEI_CL_RFD_SIZE) + \
                           (FEI_N_RFD_LOAN * FEI_CL_RFD_SIZE) + \
                           (FEI_N_TFDS * (FEI_CFD_SIZE +sizeof(long))) + 4)

/* EEPROM control bits */

#define EE_SK           0x01            /* shift clock */
#define EE_CS           0x02            /* chip select */
#define EE_DI           0x04            /* chip data in */
#define EE_DO           0x08            /* chip data out */
#define EE_ENB	        (0x4800 | EE_CS)
/* EEPROM opcode */

#define EE_CMD_WRITE    0x05            /* WRITE opcode, 101 */
#define EE_CMD_READ     0x06            /* READ  opcode, 110 */
#define EE_CMD_ERASE    0x07            /* ERASE opcode, 111 */

#define EE_WRITE_0		0x4802
#define EE_WRITE_1		0x4806
/* EEPROM misc. defines */

#define EE_CMD_BITS     3               /* number of opcode bits */
#define EE_ADDR_BITS    6               /* number of address bits */
#define EE_DATA_BITS    16              /* number of data bits */
#define EE_SIZE         0x40            /* 0x40 words */
#define EE_CHECKSUM     0xbaba          /* checksum */

/* PC compatibility macros */

#define FEI_MEMSIZE0            0x00001000
#define FEI_INIT_STATE_MASK   (VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_BUFFERABLE)
#define FEI_INIT_STATE        (VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_BUFFERABLE_NOT)
#define UNKNOWN                 (-1)

/* 82557/9 PCI specific definitions */

/* Intel PRO-100B PCI specific definitions */
#ifndef PRO100B_PCI_VENDOR_ID
#define PRO100B_PCI_VENDOR_ID   0x8086  /* PCI vendor ID */
/*  #define PRO100B_PCI_DEVICE_ID   0x1229  xfsun delete*//* PCI device ID */
#define PRO100B_PCI_DEVICE_ID   0x1209  /* PCI device ID */
#endif    /* PRO100B_PCI_VENDOR_ID */

/* Intel InBusiness 10/100 PCI specific definitions */
#ifndef INBUSINESS_PCI_VENDOR_ID
#define INBUSINESS_PCI_VENDOR_ID   PRO100B_PCI_VENDOR_ID  /* PCI vendor ID */
#define INBUSINESS_PCI_DEVICE_ID   0x1030                 /* PCI device ID */
#endif    /* INBUSINESS_PCI_VENDOR_ID */

#endif /* INCLUDE_FEI82557END */

/* undef'ed PCI_IO_ADRS_OK here as IXP425 does not properly generate
  read/writes to IO address space, the FEI NIC also maps its IO space to 
  a memory space, and can work without IO transactions
*/
#undef PCI_IO_ADRS_OK

/* typedefs */

typedef struct pciResource              /* PCI_RESOURCES */
    {
    UINT32      iobaseCsr;              /* Base Address Register 0 */
    UINT32      membaseCsr;             /* Base Address Register 1 */
    char        irq;                    /* Interrupt Request Level */
    UINT32      irqvec;                 /* Interrupt Request vector */
    UINT32      configType;             /* type of configuration */
    void *      buf;                    /* any allocated buffer space */
    UINT32      cpuToPciOffset;         /* Any offset from CPU to PCI address */
    } PCI_RESOURCES;

typedef struct boardResource		/* BOARD_RESOURCES */
    {
    UINT32  type;                   /* type of the board */
    UINT32  vendorId;               /* Vendor ID */
    UINT32  deviceId;               /* Device ID */
    UINT32  decUsrFlags;            /* DEC driver user flags */
    } BOARD_RESOURCES;

#ifdef INCLUDE_FEI82557END

typedef struct feiResource              /* FEI_RESOURCE */
    {
    UINT32      membaseCsr;             /* Base Address Register 0 */
    UINT32      iobaseCsr;              /* Base Address Register 1 */
    UINT32      membaseFlash;           /* Base Address Register 2 */
    char        irq;                    /* Interrupt Request Level */
    UINT32      configType;             /* type of configuration */
    UINT32      boardType;              /* type of LAN board this unit is */
    UINT32      pciBus;                 /* PCI Bus number */
    UINT32      pciDevice;              /* PCI Device number */
    UINT32      pciFunc;                /* PCI Function number */
    UINT16      eeprom[0x40];           /* Ethernet Address of this unit */
    INT32       timeout;                /* timeout for the self-test */
    INT32       str[6];                 /* storage for the self-test result */
    volatile INT32 * pResults;          /* pointer to the self-test result */
    UINT        memLength;              /* required memory size */
    UINT        initialStateMask;       /* mask parameter to vmStateSet */
    UINT        initialState;           /* state parameter to vmStateSet */
    } FEI_RESOURCE;

#endif


/* locals */

/*
 * This array defines the board-specific PCI resources, the base address
 * register configuration mode and the Ethernet adapter type. It's indexed
 * using the device number returned from pciFindDevice().
 *
 * The mode is set as AUTO so this will be erased by the configuration read
 * from the card that is effectively set by pciAssignResources(). See
 * sysLanPciInit() for this.
 */

LOCAL PCI_RESOURCES pciResources [IXP425_PCI_MAX_DEV] =
    {
    {PCI_IO_ADR0, PCI_MEM_ADR0, PCI_INT_LVL0, PCI_INT_VEC0, PCI_REG_MOD, 0, 0},
    {PCI_IO_ADR1, PCI_MEM_ADR1, PCI_INT_LVL1, PCI_INT_VEC1, PCI_REG_MOD, 0, 0},
    {PCI_IO_ADR2, PCI_MEM_ADR2, PCI_INT_LVL2, PCI_INT_VEC2, PCI_REG_MOD, 0, 0},
    {PCI_IO_ADR3, PCI_MEM_ADR3, PCI_INT_LVL3, PCI_INT_VEC3, PCI_REG_MOD, 0, 0}
    };

/*
 * This array defines board-specific vendor and device ids, flags to pass to
 * the drive load routine and the function used to select the media.
 */

LOCAL BOARD_RESOURCES boardResources [] =
    {
#ifdef INCLUDE_FEI82557END

    {PRO100B, PRO100B_PCI_VENDOR_ID, PRO100B_PCI_DEVICE_ID, 0},
    {INBUSINESS, INBUSINESS_PCI_VENDOR_ID, INBUSINESS_PCI_DEVICE_ID, 0},

#ifdef INCLUDE_FEI_UNTESTED
    {XX82559ER, PRO100B_PCI_VENDOR_ID, I82559ER_PCI_DEVICE_ID, 0},
#endif

#endif /* INCLUDE_FEI82557END */
    };

/* END load strings */

LOCAL char	endLoadStr[IXP425_PCI_MAX_DEV][END_LD_STR_SIZE];

/* Index of devices */

LOCAL int       currentEndDevice        = 0;


#ifdef INCLUDE_FEI82557END

LOCAL UINT32 feiUnits;                  /* number of FEIs we found */

LOCAL FEI_RESOURCE feiResources [IXP425_PCI_MAX_DEV] =
    {
    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},

    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},

    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE},

    {UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, {UNKNOWN}, UNKNOWN,
     {UNKNOWN}, NULL, FEI_MEMSIZE0, FEI_INIT_STATE_MASK, FEI_INIT_STATE}
    };

LOCAL const char * phys[] =
    {
    "None", "i82553-A/B", "i82553-C", "i82503",
    "DP83840", "80c240", "80c24", "i82555",
    "unknown-8", "unknown-9", "DP83840A", "unknown-11",
    "unknown-12", "unknown-13", "unknown-14", "unknown-15"
    };

enum phy_chips
    {
    NonSuchPhy=0, I82553AB, I82553C, I82503,
    DP83840, S80C240, S80C24, I82555, DP83840A=10, UndefinedPhy
    };

LOCAL const char *connectors[] = {" RJ45", " BNC", " AUI", " MII"};

#endif /* INCLUDE_FEI82557END */

/* imports */

/* End device table - should be IXP425_PCI_MAX_DEV+1 entries */

IMPORT END_TBL_ENTRY	endDevTbl[];
IMPORT unsigned char sysMacBase[];

#ifdef INCLUDE_FEI82557END

/* FEI specific imports */

IMPORT FUNCPTR  feiEndIntConnect;
IMPORT FUNCPTR  feiEndIntDisconnect;
IMPORT END_OBJ* fei82557EndLoad (char *, void *);
IMPORT void	sysFlashBoardDelay (void);
/*extern void sysDelay(void);*/
extern void sysMicroDelay(int microseconds);
/* forward declarations */

extern void printpxu(char *nameptr, unsigned int value);

LOCAL UINT16    sys557eepromRead (int unit, int location);
LOCAL UINT32    sys557mdioRead   (int unit, int phyId, int location);
LOCAL UINT32    sys557mdioWrite  (int unit, int phyId, int location, int value);
LOCAL int       sys557IntEnable  (int unit);
LOCAL int       sys557IntDisable (int unit);
LOCAL int       sys557IntAck     (int unit);
UINT32 sys557EndPhysToPci ( int	unit, UINT32 PhysAddr);
UINT32 sys557EndPciToPhys ( int	unit, UINT32 PhysAddr);

#endif /* INCLUDE_FEI82557END */

#define SWAP16(x) ((((x) << 8) | ((x) >> 8)) & 0xFFFF)
#define SWAP32(x)               \
  (((x) << 24) |                \
  (((x) & 0x0000FF00) << 8) |   \
  (((x) & 0x00FF0000) >> 8) |   \
  (((unsigned int)(x)) >> 24))


#ifdef PCI_IO_ADRS_OK
#define sysPciOutWord(addr,data)   PCI_OUT_WORD((void*)(addr-IXP425_PHYS_PCI_IO_BASE),data)
#define sysPciOutLong(addr,data)   PCI_OUT_LONG((void*)(addr-IXP425_PHYS_PCI_IO_BASE),data)
#else
#ifdef IXP425_PCI_ENABLE_BYTE_ROUTING
#define sysPciOutWord(addr,data)   *(volatile UINT16*)((addr)) = SWAP16((UINT16)data)
#define sysPciOutLong(addr,data)   *(volatile UINT32*)((addr)) = SWAP32((UINT32)data)
#else
#define sysPciOutWord(addr,data)   *((volatile UINT16*)((addr) & ~3)) = (UINT16)data
#define sysPciOutLong(addr,data)   *(volatile UINT32*)((addr)) = (UINT32)data
#endif
#endif /*PCI_IO_ADRS_OK*/

/*because we do not return read values as return codes in our
  pci IO config library, we must define these as functions, not macros*/
UINT16 sysInWord(ULONG addr)
{
#ifdef PCI_IO_ADRS_OK
    UINT16 retval;
    pciIOInWord((void*)(addr-IXP425_PHYS_PCI_IO_BASE), &retval);
    return retval;
#else

    UINT32 val;
    UINT16 retval;
    if (addr & 3)
    {
	addr=addr & ~3; /*round down to 32 bit align*/
	val = *((UINT32*)addr);
#ifdef IXP425_PCI_ENABLE_BYTE_ROUTING
	val = SWAP32(val); 
#endif
	retval = val >> 16;
	return retval;
    }
    else
    {
	return *((UINT16*)addr);
    }

#endif /*PCI_IO_ADRS_OK*/
}

ULONG sysInLong(ULONG addr)
{
#ifdef PCI_IO_ADRS_OK
    ULONG retval;
    pciIOInLong((void*)(addr-IXP425_PHYS_PCI_IO_BASE), &retval);
    return retval;
#else
#ifdef IXP425_PCI_ENABLE_BYTE_ROUTING
    return SWAP32(*((ULONG*)addr));
#else
    return *((ULONG*)addr);
#endif
#endif
}



/*******************************************************************************
*
* sysLanPciInit - prepare LAN adapter for initialization