fei82557end.c

INTEL IXP425的VXWORKS BSP

#define DRV_DEBUG_LOAD          0x0010
#define DRV_DEBUG_IOCTL         0x0020
#define DRV_DEBUG_INT           0x0040
#define DRV_DEBUG_START         0x0080
#define DRV_DEBUG_DUMP          0x0100
#define DRV_DEBUG_PHY           0x0200
#define DRV_DEBUG_ALL           0xffff


int     fei82557Debug = DRV_DEBUG_ALL;


#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)                        \
    do {                                                                \
    if (fei82557Debug & FLG)                                            \
        if (_func_logMsg != NULL)                                       \
            _func_logMsg (X0, (int)X1, (int)X2, (int)X3, (int)X4,       \
                            (int)X5, (int)X6);                          \
    } while (0)


#else /* DRV_DEBUG557 */


#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)
#define DRV_PRINT(FLG, X)


#endif /* DRV_DEBUG557 */


/* general macros for reading/writing from/to specified locations */


#if (_BYTE_ORDER == _BIG_ENDIAN)
 
#define FEI_SWAP_LONG(x)        LONGSWAP(x)
#define FEI_SWAP_WORD(x)        (MSB(x) | LSB(x) << 8)
 
#else
 
#define FEI_SWAP_LONG(x)        (x)
#define FEI_SWAP_WORD(x)        (x)
 
#endif /* _BYTE_ORDER == _BIG_ENDIAN */


/* Cache and PCI-bus related macros */


#define FEI_VIRT_TO_SYS(virtAddr)                                           \
        (FEI_LOCAL_TO_SYS (((UINT32) FEI_VIRT_TO_PHYS (virtAddr))))


#define FEI_VIRT_TO_PHYS(virtAddr)                                          \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheDmaFuncs, (char *)(virtAddr))


#define FEI_LOCAL_TO_SYS(physAddr)                                          \
        LOCAL_TO_SYS_ADDR (pDrvCtrl->unit, (physAddr))


#define FEI_SYS_TO_VIRT(physAddr)                                           \
        (FEI_SYS_TO_LOCAL (((UINT32) FEI_PHYS_TO_VIRT (physAddr))))


#define FEI_PHYS_TO_VIRT(physAddr)                                          \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheDmaFuncs, (char *)(physAddr))


#define FEI_SYS_TO_LOCAL(virtAddr)                                          \
        SYS_TO_LOCAL_ADDR (pDrvCtrl->unit, (virtAddr))


#define FEI_CACHE_INVALIDATE(address, len)                                  \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))


#define FEI_CACHE_FLUSH(address, len)                               \
        CACHE_DRV_FLUSH (&pDrvCtrl->cacheFuncs, (address), (len))



/* driver flags */
#define FEI_OWN_MEM     0x01            /* internally provided memory */
#define FEI_INV_NCFD    0x02            /* invalid nCFDs provided */
#define FEI_INV_NRFD    0x04            /* invalid nRFDs provided */
#define FEI_POLLING     0x08            /* polling mode */
#define FEI_PROMISC     0x20            /* promiscuous mode */
#define FEI_MCAST       0x40            /* multicast addressing mode */
#define FEI_MCASTALL    0x80            /* all multicast addressing mode */
#define FEI_MEMOWN      0x10            /* device mem allocated by driver */
 
#define FEI_FLAG_CLEAR(clearBits)                                       \
    (pDrvCtrl->flags &= ~(clearBits))


#define FEI_FLAG_SET(setBits)                                           \
    (pDrvCtrl->flags |= (setBits))


#define FEI_FLAG_GET()                                                  \
    (pDrvCtrl->flags)


#define FEI_FLAG_ISSET(setBits)                                         \
    (pDrvCtrl->flags & (setBits))


/* shortcuts */
#define END_FLAGS_ISSET(setBits)                                        \
    ((&pDrvCtrl->endObj)->flags & (setBits))


#define FEI_VECTOR(pDrvCtrl)                                            \
    ((pDrvCtrl)->board.vector)


#define FEI_INT_ENABLE(pDrvCtrl)                                        \
    ((int)(pDrvCtrl)->board.intEnable)


#define FEI_INT_DISABLE(pDrvCtrl)                                       \
    ((int)(pDrvCtrl)->board.intDisable)


#define FEI_INT_ACK(pDrvCtrl)                                           \
    ((int)(pDrvCtrl)->board.intAck)


#define RFD_SLUSH       8
#define CL_OVERHEAD     4               /* prepended cluster header */
#define CL_RFD_SIZE     (RFD_DESC_SIZE + CL_OVERHEAD + RFD_SLUSH)               


#define FEI_SAFE_MEM(pDrvCtrl)                                          \
    ((pDrvCtrl)->memSize)


#define FEI_RFD_MEM(pDrvCtrl)                                           \
    (CL_RFD_SIZE * (pDrvCtrl)->nRFDs)



#define FEI_CFD_MEM(pDrvCtrl)                                           \
    (CFD_SIZE * (pDrvCtrl)->nCFDs)


#ifdef INCLUDE_RFC_2233


#define FEI_HADDR(pEnd)                                                 \
                ((pEnd)->pMib2Tbl->m2Data.mibIfTbl.ifPhysAddress.phyAddress)


#define FEI_HADDR_LEN(pEnd)                                             \
                ((pEnd)->pMib2Tbl->m2Data.mibIfTbl.ifPhysAddress.addrLength)
#else


/* Old RFC 1213 mib2 interface */


#define FEI_HADDR(pEnd)                                                 \
        ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)


#define FEI_HADDR_LEN(pEnd)                                             \
        ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)


#endif /* INCLUDE_RFC_2233 */


/* Control Status Register definitions, some of them came from if_fei.h */


#define CSR_STAT_OFFSET         SCB_STATUS      /* CSR status byte */
#define CSR_ACK_OFFSET          0x01            /* CSR acknowledge byte */
#define CSR_COMM_OFFSET         SCB_CMD         /* CSR command byte */
#define CSR_INT_OFFSET          0x03            /* CSR Interrupt byte */
#define CSR_GP_OFFSET           SCB_POINTER     /* CSR General Pointer */
#define CSR_PORT_OFFSET         SCB_PORT        /* CSR PORT Register */
#define CSR_FLASH_OFFSET        SCB_FLASH       /* CSR FLASH Register */
#define CSR_EEPROM_OFFSET       SCB_EEPROM      /* CSR EEPROM Register */
#define CSR_MDI_OFFSET          SCB_MDI         /* CSR MDI Register */
#define CSR_RXBC_OFFSET         SCB_EARLYRX     /* CSR early RCV Byte Count */


/* Control Status Registers read/write macros */


/* Control Status Registers write macros */


/*
 * CSR_BYTE_WR, CSR_WORD_WR, and CSR_LONG_WR have a CACHE_PIPE_FLUSH() 
 * and CSR_BYTE_RD (CSR_INT_OFFSET, (UINT8) tmp) embedded in them.
 * The CSR_BYTE_RD is to force the write data through any write posting queues
 * it may be stuck while crossing the pci. The CACHE_PIPE_FLUSH() is necessary
 * to ensure the proper order of execution. The choice of reading the interrupt
 * mask register is not significant except that it is a convient location 
 * which has no side effects when read.
 */  


#define CSR_BYTE_WR(offset, value)                                      \
    {                                                                   \
    UINT8 tmp;                                                          \
    FEI_BYTE_WR (((UINT32) (pDrvCtrl->pCSR) + (offset)), (value));      \
    CACHE_PIPE_FLUSH();                                                 \
    CSR_BYTE_RD (CSR_INT_OFFSET, tmp);                                  \
    }   


#define CSR_WORD_WR(offset, value)                                      \
    {                                                                   \
    UINT8 tmp;                                                          \
    FEI_WORD_WR (((UINT32) (pDrvCtrl->pCSR) + (offset)), (value));      \
    CACHE_PIPE_FLUSH();                                                 \
    CSR_BYTE_RD (CSR_INT_OFFSET, tmp);                                  \
    } 


#define CSR_LONG_WR(offset, value)                                      \
    {                                                                   \
    UINT8 tmp;                                                          \
    FEI_LONG_WR (((UINT32) (pDrvCtrl->pCSR) + (offset)), (value));      \
    CACHE_PIPE_FLUSH();                                                 \
    CSR_BYTE_RD (CSR_INT_OFFSET, tmp);                                  \
    } 


/* this is a special case, as the device will read it as an address */


#define CSR_GP_WR(value)                                                \
    do {                                                                \
    volatile UINT32 temp = FEI_VIRT_TO_SYS (value);                     \
                                                                        \
    CSR_LONG_WR (CSR_GP_OFFSET, (temp));                                \
    } while (0)


/* Control Status Registers read macros */


#define CSR_BYTE_RD(offset, value)                                      \
    FEI_BYTE_RD ((UINT32 *) ((UINT32) (pDrvCtrl->pCSR) + (offset)),     \
             (value))


#define CSR_WORD_RD(offset, value)                                      \
    FEI_WORD_RD ((UINT32 *) ((UINT32) (pDrvCtrl->pCSR) + (offset)),     \
             (value))


#define CSR_LONG_RD(offset, value)                                      \
    FEI_LONG_RD ((UINT32 *) ((UINT32) (pDrvCtrl->pCSR) + (offset)),     \
             (value))


/* FD rings available */
 
#define CFD_FREE                0x01            /* CFD free ring */
#define CFD_USED                0x02            /* CFD used ring */
#define RFD_FREE                0x04            /* RFD free ring */
 
#define CFD_COMM_WORD           0x01            /* CFD command word */
#define CFD_STAT_WORD           0x02            /* CFD status word */
#define RFD_COMM_WORD           0x04            /* RFD command word */
#define RFD_STAT_WORD           0x08            /* RFD status word */
 
#define CFD_ACTION              0x01            /* generic action command */
#define CFD_TX                  0x02            /* transmit command */


/* frame descriptors macros: these are generic among RFDs and CFDs */


#define FD_FLAG_ISSET(fdStat, bits)                                     \
    (((UINT16) (fdStat)) & ((UINT16) (bits)))


/* get the pointer to the appropriate frame descriptor ring */


#define FREE_CFD_GET(pCurrFD)                                           \
    ((pCurrFD) = pDrvCtrl->pFreeCFD)


#define USED_CFD_GET(pCurrFD)                                           \
    ((pCurrFD) = pDrvCtrl->pUsedCFD)


/* command frame descriptors write macros */


#define CFD_BYTE_WR(base, offset, value)                                \
    FEI_BYTE_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


#define CFD_WORD_WR(base, offset, value)                                \
    FEI_WORD_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


#define CFD_LONG_WR(base, offset, value)                                \
    FEI_LONG_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


/* this is a special case, as the device will read as an address */


#define CFD_NEXT_WR(base, value)                                        \
    do {                                                                \
    volatile UINT32 temp = (UINT32) FEI_VIRT_TO_SYS (value);            \
                                                                        \
    CFD_LONG_WR ((UINT32) (base), CFD_NEXT_OFFSET, (temp));             \
    } while (0)


/* this is a special case, as the device will read as an address */


#define CFD_TBD_WR(base, value)                                         \
    do {                                                                \
    volatile UINT32 temp;                                               \
    temp = (value == TBD_NOT_USED) ? value :                            \
                   ((UINT32) FEI_VIRT_TO_SYS ((UINT32) (value)));       \
    CFD_LONG_WR ((UINT32) (base), CFD_TBD_ADDR_OFFSET, (temp));         \
    } while (0)


/* receive frame descriptors write macros */


#define RFD_BYTE_WR(base, offset, value)                                \
    FEI_BYTE_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


#define RFD_WORD_WR(base, offset, value)                                \
    FEI_WORD_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


#define RFD_LONG_WR(base, offset, value)                                \
    FEI_LONG_WR ((UINT32 *) ((UINT32) (base) + (offset)),               \
             (value))


/* this is a special case, as the device will read as an address */


#define RFD_NEXT_WR(base, value)                                        \
    do {                                                                \
    volatile UINT32 temp = (UINT32) FEI_VIRT_TO_SYS ((UINT32) (value)); \
                                                                        \
    RFD_LONG_WR ((UINT32) (base), RFD_NEXT_OFFSET, (temp));             \
    } while (0)


/* this is a special case, as the device will read as an address */


#define RFD_RBD_WR(base, value)                                         \
    do {                                                                \
    volatile UINT32 temp;                                               \
    temp = (value == RBD_NULL_ADDR) ? value :                            \
                  ((UINT32) FEI_VIRT_TO_SYS ((UINT32) (value)));        \
    RFD_LONG_WR ((UINT32) (base), RFD_RBD_OFFSET, (temp));              \
    } while (0)



/* receive buffer descriptors write macros */


#define RBD_BYTE_WR(base, offset, value)                                \