rominit.s

INTEL IXP425的VXWORKS BSP

	ldr		r0,L$GPIO_AP_LED
	ldr		r1,L$GPIO_AP_VAL
	str		r1, [r0]


	ldr		r0,L$AP_LED_OUT
	ldr		r1,L$AP_LED_VAL
	str		r1, [r0]
	

/* Disable refresh Cycles */
	ldr		r9,L$LIXP425_SDRAM_REFRESH
	ldr		r0,L$LIXP425_SDRAM_REFRESH_DISABLE
	str		r0, [r9, #0]		/* Disable Refresh Cycle */

	DELAY(0x4000, r0)

/* Issue a NOP Command to all SDRAM devices */
	ldr		r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr		r0, L$LIXP425_SDRAM_IR_NOP_CMD
	str		r0, [r9, #0]		/* Issue NOP cmd to SDRAM */

	DELAY(0x4000, r0)


	ldr		r9,L$LIXP425_SDRAM_REFRESH
	ldr		r0,L$LIXDP425_SDRAM_CONFIG_REFRESH_CNT
	str		r0, [r9, #0]		/* Set refresh value  */

	DELAY(0x4000, r0)

	/*ldr r0,=0xC8000000
	ldr r9,=0x00000033
	str r9,[r0]*/

/* Send a PrechargeAll Command to all SDRAM devices */
	ldr		r9,L$LIXP425_SDRAM_INSTRUCTION
	ldr		r0,L$LIXP425_SDRAM_IR_PRECHARGE_ALL_CMD
	str		r0, [r9, #0]	/* Precharge all */
	DELAY(0x4000, r0)


/* Send 8 AutoRefresh Command. There should Trc cycles between every AutoRefresh */
/* Trc = 70ns for devices used here,  */
	ldr		r9,L$LIXP425_SDRAM_INSTRUCTION
	ldr		r0,L$LIXP425_SDRAM_IR_AUTOREFRESH_CMD
	str		r0, [r9, #0]	/* Auto Refresh #1 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #2 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #3 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #4 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #5 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #6 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #7 */
	DELAY(0x100, r0)
	str		r0, [r9, #0]	/* Auto Refresh #8 */
	DELAY(0x100, r0)

/* Send Mode Reg Set Cmd with CAS Latency 2 */
	ldr		r9,L$LIXP425_SDRAM_INSTRUCTION
 	ldr		r0,L$LIXP425_SDRAM_IR_MODE_SET_CAS3_CMD   
/*	ldr		r0,L$LIXP425_SDRAM_IR_MODE_SET_CAS2_CMD */
	str		r0, [r9, #0]	/* Send Mode Select Command */
	DELAY(0x4000, r0)

	ldr		r9,L$LIXP425_SDRAM_INSTRUCTION
	ldr		r0,L$LIXP425_SDRAM_IR_NORMAL_OPERATION_CMD
	str		r0, [r9, #0x00000000]	        /* Issue aNormal Operation command */
	DELAY(0x4000, r0)    

#endif /* INIT_SDRAM */

#if DEBUG_UART
	ldr r0 ,_debugStr6
	bl FUNC(UARTVString)
#endif

/*************** SDRAM Config Complete *******************************************/


	/* DebugOutVal INFO_CODE_9 */
	/*	mov		r0, #0x0009
	bl		FUNC(SevenSegDisplay)   */



/* Enable Coprocessors access */

        ldr             r0, =0x001
        mcr             p15, 0, r0, c15, c1, 0

        mcr             p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT(r0)				/* wait for the write to happen */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr             p15, 0, r0, c7, c7, 0
	CPWAIT(r0)				/* Wait */

/*
 * Set the CS0 setting for Flash to optimum timings.
 */
	ldr	r0,L$LIXP425_EXP_CS0_REG
	ldr	r1,L$LIXDP425_FLASH_CS_DEFAULT
	str	r1,[r0]


	/* DebugOutVal INFO_CODE_C */
/*	mov		r0, #0x000c
	bl		FUNC(SevenSegDisplay)   */


/*** Enable Write Buffer Coalescing ***/

#if XSCALE_WB_COAL_ENABLE
	mcr		p15, 0, r0, c7, c10, 4  	/* Drain write/fill buffers */
	CPWAIT(r0)					/* wait for the write to happen */
	CPWAIT(r0)					/* wait for the write to happen */

	mrc		p15, 0, r0, c1, c0, 1   	/* Read Auxiliary Control Reg */
	and		r0, r0, #0xfffffffe    	/* Enable Coalescing */
	mcr		p15, 0, r0, c1, c0, 1  	/* Write Auxiliary Control Reg */
	CPWAIT(r0)					/* wait for the write to happen */

	NOP
	NOP
#endif

warm_start:

	
/* Disable Interrupts */
        MRS     r1, cpsr                		/* get current status */
        ORR     r1, r1, #I_BIT | F_BIT  	/* disable IRQ and FIQ */
        MSR     cpsr, r1

/* Interrupts Disabled */

        ldr     r0, =IXP425_ICMR  /* Zero-out Interrupt Mask */
        mov     r2, #0x0
        str     r2, [r0]

/* 3: Jump to here + New FLash Location */
/* We could jump upto location in Flash,
 * But we have already copied enough code to
 * low ram to continue code execution from here
 */

	ldr	r0,=IXP425_EXPANSION_BUS_BASE2
        orr	r0,r0,pc
	mov	pc,r0          

/* 4: Write to Expansion Bus controller to swap Flash & Ram */

	ldr	r0,=IXP425_EXP_CNFG0
	ldr	r1,L$LIXDP425_EXP_CNFG0_VAL
/*	ldr	r1,[r0]  */
/*	and	r1,r1,#0x7FFFFFFF  */
/*	and	r1,r1,#0x7FFFFFEE  */
	str	r1,[r0]                                
/*
 * End of switch , should now be running in Flash in its relocated position.
 */

	/* DebugOutVal INFO_CODE_D */
/*	mov		r0, #0x000d
	bl		FUNC(SevenSegDisplay)   */

/* Enable Coprocessors access */
        ldr     r0, =0x001
        mcr     p15, 0, r0, c15, c1, 0

        mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT(r0)				/* wait for the write to happen */

#ifdef ROM_ENABLES_MMU

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr     p15, 0, r0, c7, c7, 0
	CPWAIT(r0)			/* Wait */

/* If Enable Instruction Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr     r0, r0, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
	CPWAIT(r0)			/* Wait */

/* Set Translation Table Base */
        ldr     r0, =MMU_TRANSLATION_BASE
        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */

/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/
	CPWAIT(r0)			/* Wait */

/* Set Domain Access Control Register */
        ldr     r0, =0xffffffff         /* Set All 16 domains to manager access */
        mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions */

/* Enable MMU */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register */
        orr     r0, r0, #0x00000001     /* Enable MMU */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */
	CPWAIT(r0)			/* Wait */

/* Drain Write/Fill Buffers */
        mcr     p15, 0, r0, c7, c10, 4  /* Drain */
	CPWAIT(r0)			/* Wait */

/* Enable Data Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000004             /* Enable Data Cache */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */
	CPWAIT(r0)			/* Wait */

#endif /* ROM_ENABLES_MMU */

/* Enable Branch Target Buffer */   /* xfsun comment*/
/*        mrc     p15, 0, r0, c1, c0, 0 */  /* Read Control Reg */
/*        orr     r0, r0, #0x00000800        */     /* Enable BTB */
/*        mcr     p15, 0, r0, c1, c0, 0 */  /* Write Back the Control Reg */
/*	CPWAIT(r0)	*/		/* Wait */

/******************************************************************************/
/******************************************************************************/

	/* DebugOutVal INFO_CODE_E */
/*	mov		r0, #0x000e
	bl		FUNC(SevenSegDisplay)   */

	
vxWorks_boot:

	ldr		r0,L$GPIO_WLAN_LED
	ldr		r1,L$GPIO_WLAN_VAL
	str		r1, [r0]

		
	
/*  Now jump to the code that starts the whole vxWorks boot process */

	mov	r0, r8
	
	ldr	sp, L$STACK_ADDR
	ldr	pc, L$StrtInFlash  
	
/******************************************************************************/
/******************************************************************************/


_ARM_FUNCTION(SevenSegDisplay)

	ldr r6,L$LED_DISPLAY
	strh	        r0, [r6]
	mov	        pc, lr


/************************** UART Helpers ******************************************/

_ARM_FUNCTION(UARTVString)

/* Do nothing as byte reads from flash not allowed */
	mov	        pc, lr     


        ldr             r10, =IXP425_UART2_BASE

UARTNextChar:
        ldrb            r1, [r0], #1
        teq             r1, #0
        beq             URATTxDone


        /* UARTTextOut     r10, r1, r2 */
        and             r1, r1, #0xff

/* Modified, don't even check if there is room in the transfer fifi`o just jut it.. TODO : remove later, on real card */
/*
        ldr             r10, =IXP425_UART2_BASE
        ldr             r2, [r10, #UART_LineStatus]
        TST             r2. #UARTLSR_TXHoldingEmpty
        BEQ             10b
*/
        str             r1, [r10, #UART_Transmit] /* strb */

/*Start-  Included to slow down writes to simultor : TODO: Remove later */
	DELAY(0x200, r3)
/*End-  Included to slow down writes to simultor : TODO: Remove later */

        B               UARTNextChar

URATTxDone:
        mov             r1, #13
        /* UARTTx          r10, r1, r2 */
        mov             r1, #10
        str             r1, [r10, #UART_Transmit] /* strb */
        /* UARTTx          r10, r1, r2 */
        str             r1, [r10, #UART_Transmit] /* strb */
	mov	        pc, lr

/*
Better don't use r0, r1, r2 and r10s
Uses r0, r10
*/
UARTStart:
	ldr	        r10, =IXP425_UART2_BASE
	ldr	        r0, =UART_DMABodgeDelay

UARTDelay:
	subs	        r0, r0, #1
	bne	        UARTDelay

    /* enable access to divisor registers */

	mov	        r0, #UARTLCR_DivisorLatchAccess
	str	        r0, [r10, #UART_LineControl] /* strb */

	ldr	        r0, =UART_DMABodgeDelay

UARTDelay1:
	subs	        r0, r0, #1
	bne	        UARTDelay1

    /* select baud rate */
/* 115200 Baud */
	ldr	        r0, =BaudRateDivisor_115200 	 
	strb	        r0, [r10, #UART_DivisorLatchLSB] 
	mov	        r0, r0, LSR #8 			 
	strb	        r0, [r10, #UART_DivisorLatchMSB] 

	ldr	        r0, =BaudRateDivisor_9600
	str	        r0, [r10, #UART_DivisorLatchLSB] /*strb  */
	mov	        r0, r0, LSR #8
	str	        r0, [r10, #UART_DivisorLatchMSB]  /* strb */

    /* 8 data, 1 stop, no parity */
	mov	        r0, #UARTLCR_CharLength8 | UARTLCR_StopBits1

    /* also disable access to divisor regs */
	str	        r0, [r10, #UART_LineControl] /* strb */

    /* no irqs , but enable the UART on IXP425 */
	mov	        r0, #0x40
	str	        r0, [r10, #UART_InterruptEnable] /* strb */

	mov             r0, #UARTFCR_Enable
	str            r0, [r10, #UART_FIFOControl] /* strb */
	/* turn fifos on */
	mov             r0, #UARTFCR_RXReset | ARTFCR_TXReset | UARTFCR_Mode0RXRDYTXRDY | UARTFCR_RXTrigger1
	str            r0, [r10, #UART_FIFOControl] /* strb */

    /* make DTR active, RTS inactive, stop other end */
	mov	        r0, #UARTMCR_DTRActive
	str	        r0, [r10, #UART_ModemControl] /* strb */

	mov	        pc, lr


_debugStr1: .asciz  "IXP425 Uart initialized"
_debugStr2: .asciz  "IXP425 Memory Config 32 Mbytes"
_debugStr3: .asciz  "IXP425 Memory Config 64 Mbytes"
_debugStr4: .asciz  "IXP425 Memory Config 128 Mbytes"
_debugStr5: .asciz  "IXP425 Memory Config  Error"
_debugStr6: .asciz  "IXP425 Memory Config Complete"
_debugStr7: .asciz  "IXP425 Memory Config 256 Mbytes"

	.align 4

/* TODO: Resolve these addresses for real. */
L$StrtInRam:    .long   FUNC(romStart) - FUNC(romInit)

L$StrtInFlash:	.long   ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$STACK_ADDR:	.long	STACK_ADRS

L$FlashDramSwapSize: .long  BOOT_ROM_RELOCATE_SIZE

L$LIXP425_EXP_CS0_REG:				.long	IXP425_EXP_CS0_REG
L$LIXDP425_FLASH_CS_DEFAULT:			.long	IXDP425_FLASH_CS_DEFAULT

/* SDRAM Literals */
L$LIXP425_SDRAM_CONFIG_BASE:			.long	IXP425_SDRAM_CONFIG_BASE
/* L$LSDRAM_CONFIG_32MEG:				.long	SDRAM_CONFIG_32MEG   */
L$LSDRAM_CONFIG_32MEG:				.long	0x00000000
L$LSDRAM_CONFIG_64MEG:				.long   SDRAM_CONFIG_64MEG
L$LSDRAM_CONFIG_128MEG:				.long	SDRAM_CONFIG_128MEG
L$LSDRAM_CONFIG_256MEG:				.long	SDRAM_CONFIG_256MEG
L$LIXP425_SDRAM_CONFIG:				.long   IXP425_SDRAM_CONFIG

L$LIXP425_SDRAM_REFRESH: 			.long 	IXP425_SDRAM_REFRESH
L$LIXP425_SDRAM_REFRESH_DISABLE:		.long 	IXP425_SDRAM_REFRESH_DISABLE
L$LIXP425_SDRAM_INSTRUCTION:			.long   IXP425_SDRAM_INSTRUCTION
L$LIXP425_SDRAM_IR_NOP_CMD:			.long   IXP425_SDRAM_IR_NOP_CMD
L$LIXDP425_SDRAM_CONFIG_REFRESH_CNT:		.long   IXDP425_SDRAM_CONFIG_REFRESH_CNT
L$LIXP425_SDRAM_IR_PRECHARGE_ALL_CMD:		.long   IXP425_SDRAM_IR_PRECHARGE_ALL_CMD
L$LIXP425_SDRAM_IR_AUTOREFRESH_CMD:		.long   IXP425_SDRAM_IR_AUTOREFRESH_CMD
/*sun xingfang added 23/july/2003 */
L$LIXP425_SDRAM_IR_MODE_SET_CAS2_CMD:		.long   IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
L$LIXP425_SDRAM_IR_MODE_SET_CAS3_CMD:		.long   IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
L$LIXP425_SDRAM_IR_NORMAL_OPERATION_CMD:	.long   IXP425_SDRAM_IR_NORMAL_OPERATION_CMD



/* DebugOutInitLiteral */
L$CS2_REG: .long 0xc4000008
L$CS2_VAL: .long 0xBFFF0002     
/* L$CS2_VAL: .long 0x00000000   */

L$GPIO_AP_LED: .long 0xc8004000
L$GPIO_AP_VAL: .long 0x00002400

L$AP_LED_OUT: .long 0xc8004004
L$AP_LED_VAL: .long 0x0000039F

L$GPIO_WLAN_LED: .long 0xc8004000
L$GPIO_WLAN_VAL: .long 0x00003400

L$LIXDP425_EXP_CNFG0_VAL: .long 0x007FFFEE

L$LED_DISPLAY: .long 0xC8000000