rominit.s

INTEL IXP425的VXWORKS BSP

/* romInit.s - vxWorks ixdp425 initialization module */

/* Copyright 2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,04apr03,m_h  enable BTB
01e,30jan03,jb3  Fix SPR 85040 Serialdata corruption.
01d,24sep02,jb3  Going for the Csr_Gold
01c,24sep02,jb  Changing memory timing
01b,12jun02,jb  Continuing restructure
01a,05jun02,jb  initial version...
*/

#define _ASMLANGUAGE

#include "vxWorks.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"

#include "ixp425.h"
#include "ixdp425.h"
/* macros fail in diab #include "debugutils.h" */


#include "sysLib.h"
#include "config.h"


	.data
        .globl  FUNC(copyright_wind_river)
        .long   FUNC(copyright_wind_river)

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call the
generic C routine romStart() with parameter BOOT_COLD.

The routine romInit() masks interrupts in the processor, initialises
the MMU, sets the initial stack pointer (to STACK_ADRS which is defined
in configAll.h) and initialises system hardware including configuring
the DRAM controller. Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.

The IXP425 device has a mechansim to "swap" the Expansion bus CS0 and SDRAM
decode spaces. i.e RAM can be moved to zero (where the vectors live)
without resorting to the use of the MMU.


The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot". This
entry point allows a parameter to be passed to romStart().
It first has to disable the MMU, though, as romInit will disable it
during initialization.

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "IXP425 Data Manual,"
*/

#define INIT_SDRAM	 (1)
#define XSCALE_WB_COAL_ENABLE (1)
/* debug routines */
#define IMMED1 #1
#define DELAY(cycles, reg0)	\
	ldr	reg0, = cycles ;	\
	subs	reg0, reg0, IMMED1 ;	\
	subne	pc,	pc, IMMED12 ;
/* 040421 james removed*/
#if 0
#define DEBUG_UART 			(1)  /* Enable Debug uart output */
#endif

#define UART_REG_SPREAD (2)
#define UART_DMABodgeDelay              10
#define UARTLCR_DivisorLatchAccess (1<<7)
#define UART_LineControl           (0x03  << UART_REG_SPREAD)
#define BaudRateDivisor_115200     1
#define BaudRateDivisor_9600       0x60
#define UART_DivisorLatchLSB       ( 0x00 << UART_REG_SPREAD )
#define UART_DivisorLatchMSB       ( 0x01 << UART_REG_SPREAD )
#define UARTLCR_CharLength8        (3<<0)
#define UARTLCR_StopBits1          (0<<2)
/* #define UART_InterruptEnable       0x01    xfsun comment */
#define UART_InterruptEnable       0x04
#define UARTFCR_Enable	           (1<<0)
#define UART_FIFOControl           (0x02 << UART_REG_SPREAD )
#define UARTFCR_RXReset            (1<<1)
#define ARTFCR_TXReset             (1<<2)
#define UARTFCR_Mode0RXRDYTXRDY    (0<<3)
#define UARTFCR_RXTrigger1         (0<<6)
#define UARTMCR_DTRActive          (1<<0)
#define UART_ModemControl          (4 << UART_REG_SPREAD )
#define UART_LineStatus            (5 << UART_REG_SPREAD )
#define UART_Transmit              (0  << UART_REG_SPREAD )
#define UARTLSR_TXHoldingEmpty     (1<<5)



        .data
        .align 4

        .globl  VAR(sdata)

VAR_LABEL(sdata) .asciz  "start of data seg"


        .text
        .align 4

        /* externals */
        .extern FUNC(romStart)
        .extern FUNC(sysPhysMemSize)

        /* globals */
        .globl  FUNC(romInit)
        .globl  _romInit
	.globl	_vectorTable
	.globl	FUNC(sysRomVecUndefInstuc)
	.globl	FUNC(sysRomVecSoftwareInt)
	.globl	FUNC(sysRomVecPrefetchAbort)
	.globl	FUNC(sysRomVecDataAbort)
	.globl	FUNC(sysRomVecUnknow)
	.globl	FUNC(sysRomVecIRQ)
	.globl	FUNC(sysRomVecFIQ)
	.globl	FUNC(sysRomVecDefault)
	.globl  FUNC(SevenSegDisplay)
	.globl  FUNC(UARTVString)
	.globl  vxWorks_boot
	.globl  FUNC(binArrayStart)
	.globl  FUNC(binArrayEnd)


_start:

/*******************************************************************************
*
* vectorTable - vector jump tabel
*
*/

/* All vectors destroys r0, r1, and r2 */

	/* Register Usage:
	* r0 contains the vector number but used for temp use
	* r1 should contain the vector number in 7seg format
	* r2 Used for temp use
	*/

_vectorTable:
        ldr     pc, =0x1000
        B       FUNC(sysRomVecUndefInstuc)
        B       FUNC(sysRomVecSoftwareInt)
        B       FUNC(sysRomVecPrefetchAbort)
        B       FUNC(sysRomVecDataAbort)
        B       FUNC(sysRomVecUnknow)
        B       FUNC(sysRomVecIRQ)
        B       FUNC(sysRomVecFIQ)

_ARM_FUNCTION(sysRomVecUndefInstuc)
        ldr     pc, UNDEFINSInt

_ARM_FUNCTION(sysRomVecSoftwareInt)
        ldr     pc, SOFTWAREINTIsr

_ARM_FUNCTION(sysRomVecPrefetchAbort)
        ldr     pc, PREFETCHABORTIsr

_ARM_FUNCTION(sysRomVecDataAbort)
        ldr     pc, VECDATAABORTIsr

_ARM_FUNCTION(sysRomVecUnknow)
        ldr     pc, UNKNOWVECIsr

_ARM_FUNCTION(sysRomVecIRQ)
        ldr     pc, IRQRAMIsr

_ARM_FUNCTION(sysRomVecFIQ)
        ldr     pc, FIQRAMIsr

	.balign 0x100
UNDEFINSInt:
	.long FUNC(sysRomVecUndefInstuc)

SOFTWAREINTIsr:
	.long FUNC(sysRomVecSoftwareInt)

PREFETCHABORTIsr:
	.long FUNC(sysRomVecPrefetchAbort)

VECDATAABORTIsr:
	.long FUNC(sysRomVecDataAbort)

UNKNOWVECIsr:
	.long FUNC(sysRomVecUnknow)

IRQRAMIsr:
	.long FUNC(sysRomVecIRQ)

FIQRAMIsr:
	.long FUNC(sysRomVecFIQ)

	.balign 0x1000

/* any data added here should reflect in ROM_TEXT_BASE in Makefile as well as in config.h */

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* This is the start of the ROM code.  The CPU will vector here upon reset.
*
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
*
* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*
* Register r8 holds startType until jump to the code that starts the whole
* vxWorks boot process
*
*/

_ARM_FUNCTION(romInit)
_romInit:
cold:
        MOV     r0, #BOOT_COLD   /* fall through to warm boot entry */




warm:
        B       bootStart

        /* copyright notice appears at beginning of ROM (in TEXT segment) */
        .ascii  "Copyright 2000 Wind River Systems, Inc. "
        .align 4

bootStart:
        MOV     r8, r0           /* store off startType */


        /* disable interrupts in CPU and switch to SVC32 mode */

        MRS     r1, cpsr
        BIC     r1, r1, #MASK_MODE
        ORR     r1, r1, #MODE_SVC32 | I_BIT | F_BIT
        MSR     cpsr, r1


        /*
         * CPU INTERRUPTS DISABLED
         *
         * Set processor and MMU to known state as follows (we may have not
         * been entered from a reset):
         *
         * MMU Control Register layout.
         *
         * bit
         *  0 M 0 MMU disabled
         *  1 A 0 Address alignment fault disabled, initially
         *  2 C 0 Data cache disabled
         *  3 W 0 Write Buffer disabled
         *  4 P 1 Should Be One (PROG32 on earlier CPUs)
         *  5 D 1 Should Be One (DATA32 on earlier CPUs)
         *  6 L 1 Should Be One (Late abort on earlier CPUs)
         *  7 B 1 Little-endian  ( Turn no Big Endian mode )
         *  8 S 0 System bit to zero } Modifies MMU protections, not really
         *  9 R 0 ROM bit to one     } relevant until MMU switched on later.
         * 10 F 0 Should Be Zero
         * 11 Z 0 Should Be Zero (Branch prediction control on 810)
         * 12 I 0 Instruction cache disabled
         *
         * Setup MMU Control Register
         */

        /* MOV     r1, #MMU_INIT_VALUE  */
        MOV     r1, #0x1080
        MCR     CP_MMU, 0, r1, c1, c0, 0        /* Write to MMU CR */

	NOP
	NOP
	NOP
	NOP
	NOP


	/* Init T+S registers, to provide output DebugOutInit */
	ldr		r0,L$CS2_REG
	ldr		r1,L$CS2_VAL
	str		r1,[r0]


	/* DebugOutVal INFO_CODE_1 */
/*	mov		r0, #0x0001
	bl		FUNC(SevenSegDisplay)  */



        /*
         * MMU is now off => addresses are physical addresses, no protection.
         *
         * If MMU was on before this, then we'd better hope it was set up
         * for flat translation (at least of this code) or there will
         * be problems. The next three instructions will still be
         * fetched "translated".
         *
         * Set Process ID Register to zero, this effectively disables
         * the process ID remapping feature.
         */

        MOV     r1, #0
        MCR     CP_MMU, 0, r1, c13, c0, 0

        MRC     CP_MMU, 0, r7, c0, c0, 0
        AND     r7,r7,#0xF



/*** Disable Write Buffer Coalescing ***/
	mcr		p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT(r0)				/* wait for the write to happen */
	CPWAIT(r0)				/* wait for the write to happen */

	mrc		p15, 0, r0, c1, c0, 1   /* Read Auxiliary Control Reg */
	orr		r0, r0, #0x00000001     /* Disable Coalescing */
	mcr		p15, 0, r0, c1, c0, 1   /* Write Auxiliary Control Reg */
	CPWAIT(r0)				/* wait for the write to happen */

	NOP
	NOP

/* fall through to warm boot entry */
        cmp     r8, #BOOT_COLD
        bne     warm_start

/* End of BUS0, First Access to & Segment DebugOutVal INFO_CODE_1 */
/*	mov		r0, #0x0001
	bl		FUNC(SevenSegDisplay)  */


/*establish UART for debug... */
        bl              UARTStart

#if DEBUG_UART
	ldr r0 ,_debugStr1
	bl FUNC(UARTVString)
#endif

/*040421 james changed*/
#if 1

	ldr r1,=0xC8001004
	ldr r9,=0x00000040
	str r9,[r1]

	ldr r1,=0xC800100c
	ldr r9,=0x00000083
	str r9,[r1]
	
	ldr r1,=0xC8001000
	ldr r9,=0x00000008
	str r9,[r1]

	ldr r1,=0xC8001004
	ldr r9,=0x00000000
	str r9,[r1]

	ldr r1,=0xC800100c
	ldr r9,=0x00000003
	str r9,[r1]

	ldr r1,=0xC8001008
	ldr r9,=0x00000003
	str r9,[r1]

#endif
/* End of BUS1 DebugOutVal INFO_CODE_2 */
/*	mov		r0, #0x0002
	bl		FUNC(SevenSegDisplay)   */



#ifdef INIT_SDRAM

	/* Put into R10 , where compare code is expecting */
/*	mov		r10,#SZ_256M   */
#if SDRAM_SIZE_128M
	mov		r10,#SZ_128M
#else
	mov		r10,#SZ_256M
#endif

	/*** DRAM Initialization ***/

	/* SDRAM Base address */
	ldr		r9,L$LIXP425_SDRAM_CONFIG_BASE

	/* Set SDRAM Base Address */

	/* Program SDRAM Bank0 Boundary  register to 256MB */
#if SDRAM_SIZE_128M
        ldr             r0, L$LSDRAM_CONFIG_128MEG
#else
	ldr             r0, L$LSDRAM_CONFIG_256MEG  
#endif

	/* SDRAM Base Config address */
	ldr		r9, L$LIXP425_SDRAM_CONFIG

	/* Store config from switch table */
        str             r0, [r9, #0]

	/* DebugOutVal INFO_CODE_7 */
/*	mov		r0, #0x0007
	bl		FUNC(SevenSegDisplay)   */


init_dram: