ixdp425.h

INTEL IXP425的VXWORKS BSP

/* ixdp425.h - IXP425 IXDP425 board header file */ 

/* Copyright 2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,23oct02,jb  Adding Chip Select 1 define for ADSL
01a,05jun02,jb  initial version...
*/

#ifndef INCixdp425h
#define INCixdp425h


#ifdef __cplusplus
extern "C" {
#endif

/*
 * SDRAM defaults. CAS latency for the "MT 48LC16M16A2 -75" parts used on IXDP425
 * is 3. For "MT 48LC16M16A2 -7E" parts use a CAS latency of 2.
 */

#define SDRAM_CONFIG_32MEG (IXP425_SDRAM_CAS_3CLKS | IXP425_SDRAM_32Meg_2Chip)
#define SDRAM_CONFIG_64MEG (IXP425_SDRAM_CAS_3CLKS | IXP425_SDRAM_64Meg_2Chip)
#define SDRAM_CONFIG_128MEG (IXP425_SDRAM_CAS_3CLKS | IXP425_SDRAM_128Meg_4Chip)
#define SDRAM_CONFIG_256MEG (IXP425_SDRAM_CAS_3CLKS | IXP425_SDRAM_256Meg_4Chip)



#define	   SZ_0	      0x00000000
#define	   SZ_1	      0x00000001
#define	   SZ_2	      0x00000002
#define	   SZ_4	      0x00000004
#define	   SZ_8	      0x00000008
#define	   SZ_16      0x00000010
#define	   SZ_32      0x00000020
#define	   SZ_64      0x00000040
#define	   SZ_128     0x00000080
#define	   SZ_256     0x00000100
#define	   SZ_512     0x00000200
#define	   SZ_1K      0x00000400
#define	   SZ_2K      0x00000800
#define	   SZ_4K      0x00001000
#define	   SZ_8K      0x00002000
#define	   SZ_16K     0x00004000
#define	   SZ_32K     0x00008000
#define	   SZ_64K     0x00010000
#define	   SZ_128K    0x00020000
#define	   SZ_256K    0x00040000
#define	   SZ_512K    0x00080000
#define	   SZ_1M      0x00100000
#define	   SZ_2M      0x00200000
#define	   SZ_4M      0x00400000
#define	   SZ_8M      0x00800000
#define	   SZ_16M     0x01000000
#define	   SZ_32M     0x02000000
#define	   SZ_64M     0x04000000
#define	   SZ_128M    0x08000000
#define	   SZ_256M    0x10000000
#define	   SZ_512M    0x20000000
#define	   SZ_1G      0x40000000
#define	   SZ_2G      0x80000000

/* 
 * Each row in SDRAM needs to be refreshed every 64ms, there are 8K rows,
 * therefore we should refresh every 7.8us according to the data sheet.
 * The refresh rate is controlled by the internal bus which operates at 133MHz.
 * => 7.8us / 7.52ns = 1037 cycles
 */
#define IXDP425_SDRAM_CONFIG_REFRESH_CNT	(0x081)
#if SDRAM_SIZE_128M
#define IXDP425_SDRAM_SIZE  (SZ_128M)
#else
#define IXDP425_SDRAM_SIZE  (SZ_256M)
#endif
#define MATACUMBE_7SEG_BASE (0x52000000 )

#define IXDP425_FLASH_CS_DEFAULT 		(0xbcd23c40)
#define IXDP425_FLASH_CS_SETTING_WR_EN 	(0xbcd23c42)
#define IXDP425_CS1_DEFAULT           (0xbfff3c03)

/*
 * GPIO lines used for I2C emulation.
 */
#define IXP425_I2C_SDA 7
#define IXP425_I2C_SCL 6


#ifdef __cplusplus
}
#endif	/* ixdp425h */

#endif