config.h

INTEL IXP425的VXWORKS BSP

 * They must be kept synchronized; effectively config.h depends on
 * Makefile. Any changes made here must be made in the Makefile and vice
 * versa.
 *
 * ROM_BASE_ADRS is the base of the Flash ROM
 * ROM_TEXT_ADRS is the entry point of the VxWorks image
 * ROM_SIZE is the size of the part of the Flash ROM allocated to the VxWorks
 *          image (block size - size of headers - NVRAM allocation)
 *
 * Two other constants are used:
 * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
 *       (uncompressed bootrom)
 * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
 *
 * The boot ROM image starts at an offset of 0 into the n'th block of flash
 * to give the diagnostics and other RTOS's room to live in.
 *
 * So the calculation for ROM_TEXT_ADRS is:
 *                         Virtual      Physical
 *   Address of Flash:     0x50000000   0x50000000
 *   Offset of nth block:  0x00000000   0x00000000  - Currently putting Bootrom at offset zero into flash 
 *   Sum:                  0x50000000   0x50000000
 *
 * Note also that the addresses given here are virtual addresses after
 * the MMU is turned on. The physical addresses will be based on zero.
 *
 * The values are given as literals here to make it easier to ensure
 * that they are the same as those in the Makefile. The build of the bootrom
 * will check that it does not overflow the space allocated.
 */

#define ROM_FLASH_BASE      	(0x50000000) 	/* Base address of CS0 in boot position */
#define ROM_FLASH_ALT_BASE      (0x50000000) 	/* Base address of CS0 in alternate position */
#define ROM_FLASH_OFFSET    	(0x0) 		/* Offset in Flash dedicated to VxWorks BSP */
#define ROM_FLASH_RESERVED	(0 * 0x00100000)		/* Size of Flash dev reserved from top */
/* #define ROM_ACTUAL_FLASH_SIZE   (16 * 0x00100000)  xfsun delete *//* Real size of Flash */
#define ROM_ACTUAL_FLASH_SIZE   (8 * 0x00100000) /* Real size of Flash */

#define ROM_BASE_ADRS       0x50040000            /* base of writable Flash */
/*   #define ROM_SIZE            0x01000000	 xfsun delete  */       /* size - start */
#define ROM_SIZE            0x00400000	          /* size - start */                                        
#define ROM_COPY_SIZE       ((ROM_SIZE - 0x2000) / 4)
#define ROM_SIZE_TOTAL      ROM_SIZE              /* total size of Flash ROM */
#define BOOT_ROM_RELOCATE_SIZE (0x00200000)

/*
 * The size must be big enough so that
 *    (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) >= size of boot image
 * We allow up to an arbitrary 128K for the image.
 */
#if (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) < 0x20000 
  #error  ROM_ values need checking in config.h/Makefile  
#endif /* (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) < 0x20000 */

#define FLASH_BASE          ROM_FLASH_ALT_BASE



/*
 * Where the text starts in ROM, (address of _romInit), normally it will be,
 * MMU_TRANSLATION_BASE + 16K + additional 1K if we are using second level
 * translation tables.
 *
 * ROM_TEXT_ADRS = MMU_TRANSLATION_BASE + 0x4000  (+ 0x400 if second level page
 *						    table used)
 */
/* Where the text starts in ROM */
#define ROM_TEXT_ADRS      0x50041000


/*
 * ISR_STACK_SIZE is defined here rather than in ../all/configAll.h (as is
 * more usual) because the stack size depends on the interrupt structure of the
 * BSP.
 */
 #define ISR_STACK_SIZE		0x1000	 /* ISR Stack Size 16 */

 #undef STACK_SAVE
 #define STACK_SAVE	 1024		 /* maximum size of stack preserved */

 #define SIZE_OF_IP_ADDRESS 24
 #define SIZE_OF_MAC_ADDRESS 6

 #define NV_BOOT_LINE_SIZE		(0x100)
 #define NV_GENERIC_STORAGE_AREA_SIZE	(0x100)

 /* 
  * These defines specify where the vxWorks bootline and end device information
  * for the board is to be stored. They are mutually exclusive and should not be
  * defined together.
  */
#define USE_EEPROM_STORAGE	/* Define this to enable eeprom as NVRAM - See ixdp425.html */

#if !defined(USE_EEPROM_STORAGE)
#error "You must eeprom nv storge enabled - enable USE_EEPROM_STORAGE"
#endif

/*
  *
  * The diagram below shows the EEPROM when used as NVRAM storage.
  * 
  +----+ Top of 512byte EEPROM.
  |    |
  |    |  MAC address storage.
  |____|_ EEPROM + 256 Bytes	-- NV_GENERIC_STORAGE_AREA
  |    |
  |    |  Boot Line Storage
  |    |
  +----+ Bottom of EEPROM	-- sysNvRamGet/sysNvRamGet - Allows access to here to 
  *
  */

 #define INCLUDE_FLASH

 #ifdef INCLUDE_FLASH   
  #define FLASH_WIDTH		2
  #define FLASH_WIDTH_SPECIAL_2     /* Special definition for Word based flash devices */
   #define SYS_FLASH_TYPE		FLASH_28F128J3A	/* Specify 16 bit 28F part */
  #define FLASH_SEGMENT_SIZE		(128 * 1024)		/* sector size of E28F128J3 */
  #define FLASH_ADRS			(ROM_FLASH_ALT_BASE + ROM_ACTUAL_FLASH_SIZE - FLASH_SEGMENT_SIZE) 
  #define FLASH_SIZE			FLASH_SEGMENT_SIZE 

  #ifdef USE_FLASH_STORAGE
    #define NV_RAM_SIZE			FLASH_SEGMENT_SIZE
    #undef  NV_BOOT_OFFSET
    #define NV_BOOT_OFFSET		(FLASH_SEGMENT_SIZE - NV_BOOT_LINE_SIZE - NV_GENERIC_STORAGE_AREA_SIZE) /* BootLine Support */
  #endif /* USE_FLASH_STORAGE */

  #define SYS_FLASH_WRITE
  #undef FLASH_NO_OVERLAY  
 #else  /* INCLUDE_FLASH */
  #define NV_RAM_SIZE		NONE
 #endif /* INCLUDE_FLASH */

#define INCLUDE_EEPROM

#ifdef INCLUDE_EEPROM
  #ifdef USE_EEPROM_STORAGE
/*     #define NV_RAM_SIZE (0x200)   */
     #define NV_RAM_SIZE (0x100)        
  #endif /* USE_EEPROM_STORAGE */
#endif /* INCLUDE_EEPROM */

/* Allocation of Generic NV storage area */  
#if defined(INCLUDE_FLASH) || defined(INCLUDE_EEPROM)
  #define NV_RAM_IF_START_OFFSET        (NV_GENERIC_STORAGE_AREA_SIZE)
  #define NV_MAC_ADDR_POOL		(NV_GENERIC_STORAGE_AREA_SIZE)		 /* Used as offset of sysNvRamGet/Set */
  #define NV_MAC_ADRS_NPE1		(NV_MAC_ADDR_POOL)
  #define NV_MAC_ADRS_NPE2		(NV_MAC_ADRS_NPE1 + SIZE_OF_MAC_ADDRESS)

  /* 
   * Most PCI NICS will store their own MAC address but we include room for them
   * here in case they don't.
   */
  #define NV_MAC_ADRS_PCIEND1		(NV_MAC_ADRS_NPE2 + SIZE_OF_MAC_ADDRESS)
  #define NV_MAC_ADRS_PCIEND2		(NV_MAC_ADRS_PCIEND1 + SIZE_OF_MAC_ADDRESS)
  #define NV_MAC_ADRS_PCIEND3		(NV_MAC_ADRS_PCIEND2 + SIZE_OF_MAC_ADDRESS)
  #define NV_MAC_ADRS_PCIEND4		(NV_MAC_ADRS_PCIEND3 + SIZE_OF_MAC_ADDRESS)

  #define NV_IP_ADRS_RESERVED           (NV_MAC_ADRS_PCIEND4 + SIZE_OF_MAC_ADDRESS)
  #define NV_IP_ADRS_NPE1               (NV_IP_ADRS_RESERVED + SIZE_OF_IP_ADDRESS)
  #define NV_IP_ADRS_NPE2               (NV_IP_ADRS_NPE1 + SIZE_OF_IP_ADDRESS)
  #define NV_IP_ADRS_PCIEND1            (NV_IP_ADRS_NPE2 + SIZE_OF_IP_ADDRESS)
  #define NV_IP_ADRS_PCIEND2            (NV_IP_ADRS_PCIEND1 + SIZE_OF_IP_ADDRESS)
  #define NV_IP_ADRS_PCIEND3            (NV_IP_ADRS_PCIEND2 + SIZE_OF_IP_ADDRESS)
  #define NV_IP_ADRS_PCIEND4            (NV_IP_ADRS_PCIEND3 + SIZE_OF_IP_ADDRESS)
   
  #define NV_RAM_IF_END_OFFSET          (NV_IP_ADRS_PCIEND4 + SIZE_OF_IP_ADDRESS)
  #define NV_RAM_IF_SIZE                (NV_RAM_IF_END_OFFSET - NV_RAM_IF_START_OFFSET)   


#endif /* defined(INCLUDE_FLASH) || defined(INCLUDE_EEPROM) */

#define INCLUDE_END			/* Enable END drivers */

#define INCLUDE_PCI			/* enable PCI Bus */
#ifdef INCLUDE_PCI
#define INCLUDE_PCI_DMA
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_END			/* If END drivers are enabled */

#define INCLUDE_FEI82557END		/* Enable Intel PCI based 8255x driver */

#ifdef INCLUDE_FEI82557END

#ifndef INCLUDE_PCI			/* Cannot have fei without pci */
#undef INCLUDE_FEI82557END
#endif /* INCLUDE_PCI */

#define IXDP_FEIEND_USE_NVRAM_IP	/* Get unassigned FEI IP addresses from NVRAM/EEPROM */
#define IXP425_MAX_FEI_DEVS IXP425_MAX_PCI_DEVS

#define IXDP_FEI557_IP0_DEFAULT		"192.168.10.1"    /* Default address for PORT0 */
#define IXDP_FEI557_IP1_DEFAULT		"192.168.20.1"    /* Default address for PORT0 */
#define IXDP_FEI557_IP2_DEFAULT		"192.168.30.1"    /* Default address for PORT0 */
#define IXDP_FEI557_IP3_DEFAULT		"192.168.40.1"    /* Default address for PORT0 */

#endif /* INCLUDE_FEI82557END */

/* define this to include IxEthAcc support */
#define INCLUDE_IXETHACCEND

#ifdef INCLUDE_IXETHACCEND

#undef  INCLUDE_IXETHACC_64BYTES_PADDING      /*  CSR silicon does the 60 bytes TX padding */

#undef INCLUDE_IXETHACC_POLL_MODE
#define IXDP_ETHACC_POLL_TICKS_PER_SECOND 1000


#define INCLUDE_IXETHACC_PORT0_END	/* enable eth phys port 0 */
#define INCLUDE_IXETHACC_PORT1_END	/* enable eth phys port 1 */

/* If IXETH_INIT_WITH_OTHER_FLAG is defined, you can specify "ixe"
 * as the bootline "other" flag to initialize it
 */
#define IXETH_INIT_WITH_OTHER_FLAG

#define IXDP_ETHACC_USE_NVRAM_MAC /* Get MAC addresses via NVRAM/EEPROM */
#undef  IXDP_ETHACC_USE_NVRAM_MAC /* Get MAC addresses via NVRAM/EEPROM */

#define IXDP_ETHACC_IP0_DEFAULT		"192.168.50.1"    /* Default address for PORT0 */
#define IXDP_ETHACC_IP1_DEFAULT		"192.168.60.1"    /* Default address for PORT1 */

/* The following IXETH and EthAcc defines are always defined */
#define IXETHACC_MBLKS 540		/* Number of allocated mBlks per IxEth */

#endif /* INCLUDE_IXETHACCEND */

/* Define INCLUDE_USER_APPL to enable Init of all network devices */
#define INCLUDE_USER_APPL

/* This is the entry point into the IXP425 Application software */
#define USER_APPL_INIT {void ixdp425AppInit(); ixdp425AppInit();}
#define INCLUDE_PING

#endif /* INCLUDE_END */

/*
 * Strictly optional components which can be removed at will
 */


#ifdef __cplusplus
}
#endif


#endif	/* INCconfigh */

#if defined(PRJ_BUILD)
 #include "prjParams.h"
#endif
/*#define IXDP_425_DEBUG*/


#if 1

 #define INCLUDE_SHELL
 #undef INCLUDE_NET_SYM_TBL
#define INCLUDE_STANDALONE_SYM_TBL

 #define INCLUDE_SHOW_ROUTINES
 #define INCLUDE_PING
 #define INCLUDE_RLOGIN
 #define INCLUDE_LOADER
 #define INCLUDE_NET_SHOW
 #define INCLUDE_UNLOADER
 
 #define INCLUDE_TELNET
 #define INCLUDE_SECURITY
 #define LOGIN_USER_NAME "flexcomm"
 #define LOGIN_PASSWORD ""
#endif