fei82557end.h

INTEL IXP425的VXWORKS BSP

 * can reap it later. We can place it after the TFD array.
 */
#define CFD_MBLK_OFFSET         CFD_TBD_OFFSET + (TBD_SIZE * TBD_MAX_FRAGS)


/*
 * This bit, if set in the FragLen field, indicates that this
 * is the last fragment that needs to be processed in this TBD.
 */
#define TBD_LASTFRAG            0x00008000

/* TX-specific bits in the status/command fields */

#define TBD_CTL_SF              0x0008          /* simple/flex mode */
#define TBD_CTL_NO_CRC          0x0010          /* no TX CRC */

#define TBD_STS_DMA_COMPLETE    0x8000          /* TX DMA done for this txcb */
#define TBD_STS_TX_OK           0x2000          /* TX done with no error */
#define TBD_STS_URUN            0x1000          /* TX underrun */

/* board specific infomation */

typedef struct
    {
    UINT32 vector;               /* interrupt vector number */
    UINT32 baseAddr;		 /* memory base address for CSR */
    UCHAR  enetAddr[6];		 /* ethernet address */
    int (*intEnable)(int unit);  /* board specific interrupt enable routine */
    int (*intDisable)(int unit); /* board specific interrupt disable routine */
    int (*intAck) (int unit);    /* interrupt ack */
    UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr);
    UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr);

    /* configuration parameters, user can override in the BSP */
    UINT8 phyAddr;  /* PHY device address, valid addresses: 0-32 */
    UINT8 phySpeed;  
    UINT8 phyDpx;
    UINT8 fill0;

    UINT16 tcbTxThresh;

    UINT16 others; /* allow you write all bits to Mode Control Register in the
	   PHY device, don't touch it unless you know what you're doing. */

    UINT32 spare1;
    UINT32 spare2;
    UINT32 spare3;
    UINT32 spare4;
    } FEI_BOARD_INFO;

typedef UINT32 *        RFD_ID;
typedef UINT32 *        RBD_ID;
typedef UINT32 *        RBD_TAG_ID;

    /* 
     * The read discriptor structure is a place holdes for the actual RFD
     * used by the device. The driver does not actuall access this area 
     * the structure but uses the macros and offsets provided. 
     */
typedef struct read_disc 
    {
    UINT32  long1;   
    UINT32  long2;
    UINT32  long3;
    UINT32  long4;
    } RD_DESC; 

    /* 
     * The RFD_TAG makes use of the additional 16 bytes of space allocated
     * for each RFD beyond the 16 bytes used by the device. This space is used
     * to store information not provided by the device but useful for managing
     * the flexible mode configuration.
     */ 

typedef struct rfd_tag
    {
    RD_DESC rfd; 		/* DON'T ACCESS this field */
    UINT16  index;
    UINT16  nextIndex;
    UINT16  spareWord;
    UINT16  status;	
    RBD_ID  pRFD;		/* pointer to own pRFD */
    UINT32  spareLong; 	
    } RFD_TAG;

    /* 
     * The RBD_TAG makes use of the additional 16 bytes of space allocated
     * for each RBD beyond the 16 bytes used by the device. This space is used
     * to store information not provided by the device but useful for managing
     * the flexible mode configuration.
     */ 
typedef struct rbd_tag
    {
    RD_DESC  rbd; 		/* DON'T ACCESS this field */
    UINT16   index;		 
    UINT16   next;
    M_BLK_ID pMblk;		 
    RFD_ID   pRFD;		/* pointer to self */
    RBD_ID   pRBD;               /* pointer to own RBD */
    } RBD_TAG; 

/* constants needed within this file */

#define FEI_MAX_UNITS	4		/* max units supported */
#define FEI_CFD_DEF	32		/* default number of CFDs */
#define FEI_RFD_DEF	32		/* default number of RFDs */
#define FEI_RFD_LOAN	8		/* number RFDs that can be loaned */
#define EH_SIZE		14  		/* avoid structure padding issues */
#define N_MCAST		12

/* SCB registers offset definitions @@@ */
#define SCB_STATUS      0x00            /* SCB status byte */
#define SCB_CMD         0x02            /* SCB command byte */
#define SCB_POINTER     0x04            /* SCB pointer */
#define SCB_PORT        0x08            /* SCB port register */
#define SCB_FLASH       0x0c            /* SCB flash control register */
#define SCB_EEPROM      0x0e            /* SCB eeprom control register */
#define SCB_MDI         0x10            /* SCB mdi control register */
#define SCB_EARLYRX     0x14            /* SCB early receive */

/* SCB Status Word byte mask definitions */

#define SCB_S_RUMASK	0x3c		/* RU status mask */
#define SCB_S_RUIDLE	0x00		/* RU is idle */
#define SCB_S_RUSUSP	0x04		/* RU is suspended */
#define SCB_S_RUNORSR	0x08		/* RU no more resources */
#define SCB_S_RURDY	0x10		/* RU is ready */
#define SCB_S_RUSUSPNR	0x24		/* RU is suspended/no more resources */
#define SCB_S_RUNORSRBD	0x28		/* RU no more resources/no more RBD's */
#define SCB_S_RURDYBD	0x30		/* RU is ready/no more RBD's */
#define SCB_S_CUMASK	0xc0		/* CU status mask */
#define SCB_S_CUIDLE	0x00		/* CU is idle */
#define SCB_S_CUSUSP	0x40		/* CU is suspended */
#define SCB_S_CUACTIVE	0x80		/* CU is active */
#define SCB_S_MASK      0xff

/* SCB STAT/ACK byte bit mask definitions */

#define SCB_S_STATMASK	0xfc00		/* stat mask */
#define SCB_S_SWI	0x0400		/* software generated interrupt */
#define SCB_S_MDI	0x0800		/* An MDI read or write cycle is done */
#define SCB_S_RNR	0x1000		/* RU left the ready state */
#define SCB_S_CNA	0x2000		/* CU left the active state */
#define SCB_S_CI	0x2000		/* CU entered the idle state */
#define SCB_S_FR	0x4000		/* RU finished receiveing a frame */
#define SCB_S_CX	0x8000		/* CU finished a cmd with I bit set */
#define SCB_S_TNO	0x8000		/* Tx command ended with not OK */

/* SCB Command byte bit mask definitions */

#define SCB_C_RUMASK	0x07		/* RU Command mask */
#define SCB_C_RUNOP	0x00		/* NOP */
#define SCB_C_RUSTART	0x01		/* RU start reception of frames */
#define SCB_C_RURESUME	0x02		/* RU resume reception of frames */
#define SCB_C_RUABORT	0x04		/* RU abort receiver immediately */
#define SCB_C_RULDHDS	0x05		/* RU load header data size */
#define SCB_C_RULDBASE	0x06		/* load RU base address */
#define SCB_C_RURBDRSM	0x07		/* RBD resume */
#define SCB_C_CUMASK	0x70		/* CU Command mask */
#define SCB_C_CUNOP	0x00		/* NOP */
#define SCB_C_CUSTART	0x10		/* CU start execution */
#define SCB_C_CURESUME	0x20		/* CU resume execution */
#define SCB_C_CULDDUMP	0x40		/* load dump counters address */
#define SCB_C_CUDUMP	0x50		/* dump stat counters */
#define SCB_C_CULDBASE	0x60		/* load CU base address */
#define SCB_C_CUDUMPRST	0x70		/* dump and reset stat counters */
#define SCB_CR_MASK     0xff

/* SCB Interrupt Control byte bit mask definitions */

#define SCB_C_M		0x01		/* interrupt mask */
#define SCB_C_SI	0x02		/* software generated interrupt */
#define SCB_C_RNR	0x10		/* RU ran out of resources */
#define SCB_C_CNA	0x20		/* CU left active state (transmit) */
#define SCB_C_FR	0x40		/* frame receive */

/* PORT commands */

#define FEI_PORT_RESET		0x0	/* PORT reset command */
#define FEI_PORT_SELFTEST	0x1	/* PORT selftest command  */
#define FEI_PORT_SELRESET	0x2	/* PORT selective reset command */
#define FEI_PORT_DUMP		0x3	/* PORT dump command */

/* Action Command Descriptions */

/* special TCB-specific command block bit mask definitions */

#define CFD_S_TX_DMA_U	0x1000		/* DMA underrun */
#define TCB_CNT_EOF	0x8000		/* all data kept in TFD */
#define CFD_C_TX_FLEX	0x0008		/* use flexible mode */


/* special Diag-specific command block bit mask definitions */

#define CFD_S_DIAG_F	0x0800		/* diag failed */

/* Command Frame Description and defines */

/* Action Status Word bit mask definitions */

#define CFD_S_OK	0x2000		/* Command completed successfully */
#define CFD_S_B         0x4000          /* CU starts access this CFD */
#define CFD_S_COMPLETE	0x8000		/* Command complete */

/* Action Command Word bit mask definitions */

#define CFD_C_NOP	0x0000		/* No Operation */
#define CFD_C_IASETUP	0x0001		/* Individual Address Setup */
#define CFD_C_CONFIG	0x0002		/* Configure Chip */
#define CFD_C_MASETUP	0x0003		/* Multicast Setup */
#define CFD_C_XMIT	0x0004		/* Transmit (see below too ...) */
#define CFD_C_DUMP	0x0006		/* Dump Registers */
#define CFD_C_DIAG	0x0007		/* Diagnose */
#define CFD_C_CID	0x1F00		/* Delay CNA interrupt */
#define CFD_C_INT	0x2000		/* 557 interrupts CPU after execution */
#define CFD_C_SUSP	0x4000		/* CU should suspend after execution */
#define CFD_C_EL	0x8000		/* End of command list */

/* 82557 Receive Frame Descriptors */

/* RFD bit mask definitions */

#define RFD_S_COLL	0x0001		/* collision during reception */
#define RFD_S_IA	0x0002		/* individual address match */
#define RFD_S_RXER	0x0010		/* receive error */
#define RFD_S_LEN	0x0020		/* type/len field designator */
#define RFD_S_SHORT	0x0080		/* frame too short */
#define RFD_S_DMA	0x0100		/* DMA Overrun failure to get bus */
#define RFD_S_RSRC	0x0200		/* received, but ran out of buffers */
#define RFD_S_ALGN	0x0400		/* received misaligned with CRC error */
#define RFD_S_CRC	0x0800		/* received with CRC error */
#define RFD_S_OK	0x2000		/* frame received successfully */
#define RFD_S_B         0x4000          /* RU begins accessing this RFD */
#define RFD_S_COMPLETE	0x8000		/* frame reception complete */

#define RFD_C_FLEX	0x0008		/* flexible mode */
#define RFD_C_HEADER	0x10		/* frame is a header */
#define RFD_C_SUSP	0x4000		/* suspend RU after receiving frame */
#define RFD_C_EL	0x8000		/* end of RFD list */

#define RFD_CNT_F	0x4000		/* actual count updated */
#define RFD_CNT_EOF	0x80		/* end of frame */

typedef UINT32 *	CL_ID;
typedef UINT32 *	FD_ID;
typedef UINT32 *	CSR_ID;
typedef FD_ID	  	CFD_ID;

/* Configuration definitions */

#define FEI_BYTE_COUNT  0x16		/* the number of Command Block bytes */
#define FEI_RX_FIFO     0x08		/* Receive FIFO limit */	
#define FEI_TX_FIFO     0x00		/* Transmit FIFO limit */	
#define FEI_ADAPT_IFS   0x00		/* Adaptive IFS */
#define FEI_MWI_ENABLE  0x01		/* Enable MWI */ 
#define FEI_RD_ALIGN    0x02            /* Read alignment Enabled */
#define FEI_RX_MAX_DMA  0x00		/* RX DMA Max Byte Count(not enabled) */
#define FEI_TX_MAX_DMA  0x00		/* TX DMA Max Byte Count(not enabled) */
#define FEI_MAX_DMA_EN  0x00		/* Enable DMA Max Byte Counts */




/* EEPROM bit definitions */

#define FEI_EESK	0x01		/* EEPROM shift clock */
#define FEI_EECS	0x02		/* EEPROM chip select */
#define FEI_EEDI	0x04		/* EEPROM data in */
#define FEI_EEDO	0x08		/* EEPROM data out */


/* Following defines should be in another header file */

/* MDI definitions */

#define MDI_READ   0x2
#define MDI_WRITE  0x1
#define MDI_CTRL_REG   0x0
#define MDI_STATUS_REG 0x1

/* MDI control register bit  */
#define MDI_CR_COLL_TEST            0x80
#define MDI_CR_FDX                  0x100       /* FDX =1, half duplex =0 */
#define MDI_CR_RESTART              0x200       /* restart auto negotiation */
#define MDI_CR_ISOLATE              0x400       /* isolate PHY from MII */
#define MDI_CR_POWER_DOWN           0x800       /* power down */
#define MDI_CR_SELECT               0x1000      /* auto speed select  */
#define MDI_CR_100                  0x2000      /* 0 = 10mb, 1 = 100mb */
#define MDI_CR_LOOPBACK             0x4000      /* 0 = normal, 1 = loopback */
#define MDI_CR_RESET                0x8000      /* 0 = normal, 1 = PHY reset */

/* MDI Status register bit definitions */
#define MDI_SR_LINK_STATUS          0x4       /* link Status -- 1 = link */
#define MDI_SR_AUTO_SELECT          0x8       /* auto speed select capable */
#define MDI_SR_REMOTE_FAULT         0x10      /* Remote fault detect */
#define MDI_SR_AUTO_NEG             0x20      /* auto negotiation complete */
#define MDI_SR_10T_HALF_DPX         0x800     /* 10BaseT half duplex capable */
#define MDI_SR_10T_FULL_DPX         0x1000    /* 10BaseT full duplex capable */
#define MDI_SR_TX_HALF_DPX          0x2000    /* TX half duplex capable */
#define MDI_SR_TX_FULL_DPX          0x4000     /* TX full duplex capable */
#define MDI_SR_T4                   0x8000    /* T4 capable */

#define PHY_100MBS      1
#define PHY_10MBS       0
#define PHY_AUTO_SPEED  2

#define PHY_FULL_DPX    1
#define PHY_HALF_DPX    0
#define PHY_AUTO_DPX    2

#define PHY_LINK_ERROR  0x10
#define PHY_AUTO_FAIL   0x20

/* PRO/100B definitions */

#define EP100B_PCI_VENDOR_ID    0x8086          /* Intel vendor ID */
#define EP100B_PCI_DEVICE_ID    0x1229          /* PRO/100B device ID */

#if ((CPU_FAMILY==I960) && (defined __GNUC__))
#pragma align 0                 /* turn off alignment requirement */
#endif	/* CPU_FAMILY==I960 */

#ifdef __cplusplus
}
#endif

#endif /* __INCfei82557Endh */